Files
@ bd21c8aa7237
Branch filter:
Location: vmkdrivers/vmkdrivers/src_9/drivers/scsi/adp94xx/adp94xx_hwi.c
bd21c8aa7237
173.3 KiB
text/x-csrc
ESXi-6.0.0b
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140 4141 4142 4143 4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172 4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364 4365 4366 4367 4368 4369 4370 4371 4372 4373 4374 4375 4376 4377 4378 4379 4380 4381 4382 4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434 4435 4436 4437 4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448 4449 4450 4451 4452 4453 4454 4455 4456 4457 4458 4459 4460 4461 4462 4463 4464 4465 4466 4467 4468 4469 4470 4471 4472 4473 4474 4475 4476 4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503 4504 4505 4506 4507 4508 4509 4510 4511 4512 4513 4514 4515 4516 4517 4518 4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538 4539 4540 4541 4542 4543 4544 4545 4546 4547 4548 4549 4550 4551 4552 4553 4554 4555 4556 4557 4558 4559 4560 4561 4562 4563 4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592 4593 4594 4595 4596 4597 4598 4599 4600 4601 4602 4603 4604 4605 4606 4607 4608 4609 4610 4611 4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646 4647 4648 4649 4650 4651 4652 4653 4654 4655 4656 4657 4658 4659 4660 4661 4662 4663 4664 4665 4666 4667 4668 4669 4670 4671 4672 4673 4674 4675 4676 4677 4678 4679 4680 4681 4682 4683 4684 4685 4686 4687 4688 4689 4690 4691 4692 4693 4694 4695 4696 4697 4698 4699 4700 4701 4702 4703 4704 4705 4706 4707 4708 4709 4710 4711 4712 4713 4714 4715 4716 4717 4718 4719 4720 4721 4722 4723 4724 4725 4726 4727 4728 4729 4730 4731 4732 4733 4734 4735 4736 4737 4738 4739 4740 4741 4742 4743 4744 4745 4746 4747 4748 4749 4750 4751 4752 4753 4754 4755 4756 4757 4758 4759 4760 4761 4762 4763 4764 4765 4766 4767 4768 4769 4770 4771 4772 4773 4774 4775 4776 4777 4778 4779 4780 4781 4782 4783 4784 4785 4786 4787 4788 4789 4790 4791 4792 4793 4794 4795 4796 4797 4798 4799 4800 4801 4802 4803 4804 4805 4806 4807 4808 4809 4810 4811 4812 4813 4814 4815 4816 4817 4818 4819 4820 4821 4822 4823 4824 4825 4826 4827 4828 4829 4830 4831 4832 4833 4834 4835 4836 4837 4838 4839 4840 4841 4842 4843 4844 4845 4846 4847 4848 4849 4850 4851 4852 4853 4854 4855 4856 4857 4858 4859 4860 4861 4862 4863 4864 4865 4866 4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887 4888 4889 4890 4891 4892 4893 4894 4895 4896 4897 4898 4899 4900 4901 4902 4903 4904 4905 4906 4907 4908 4909 4910 4911 4912 4913 4914 4915 4916 4917 4918 4919 4920 4921 4922 4923 4924 4925 4926 4927 4928 4929 4930 4931 4932 4933 4934 4935 4936 4937 4938 4939 4940 4941 4942 4943 4944 4945 4946 4947 4948 4949 4950 4951 4952 4953 4954 4955 4956 4957 4958 4959 4960 4961 4962 4963 4964 4965 4966 4967 4968 4969 4970 4971 4972 4973 4974 4975 4976 4977 4978 4979 4980 4981 4982 4983 4984 4985 4986 4987 4988 4989 4990 4991 4992 4993 4994 4995 4996 4997 4998 4999 5000 5001 5002 5003 5004 5005 5006 5007 5008 5009 5010 5011 5012 5013 5014 5015 5016 5017 5018 5019 5020 5021 5022 5023 5024 5025 5026 5027 5028 5029 5030 5031 5032 5033 5034 5035 5036 5037 5038 5039 5040 5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055 5056 5057 5058 5059 5060 5061 5062 5063 5064 5065 5066 5067 5068 5069 5070 5071 5072 5073 5074 5075 5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097 5098 5099 5100 5101 5102 5103 5104 5105 5106 5107 5108 5109 5110 5111 5112 5113 5114 5115 5116 5117 5118 5119 5120 5121 5122 5123 5124 5125 5126 5127 5128 5129 5130 5131 5132 5133 5134 5135 5136 5137 5138 5139 5140 5141 5142 5143 5144 5145 5146 5147 5148 5149 5150 5151 5152 5153 5154 5155 5156 5157 5158 5159 5160 5161 5162 5163 5164 5165 5166 5167 5168 5169 5170 5171 5172 5173 5174 5175 5176 5177 5178 5179 5180 5181 5182 5183 5184 5185 5186 5187 5188 5189 5190 5191 5192 5193 5194 5195 5196 5197 5198 5199 5200 5201 5202 5203 5204 5205 5206 5207 5208 5209 5210 5211 5212 5213 5214 5215 5216 5217 5218 5219 5220 5221 5222 5223 5224 5225 5226 5227 5228 5229 5230 5231 5232 5233 5234 5235 5236 5237 5238 5239 5240 5241 5242 5243 5244 5245 5246 5247 5248 5249 5250 5251 5252 5253 5254 5255 5256 5257 5258 5259 5260 5261 5262 5263 5264 5265 5266 5267 5268 5269 5270 5271 5272 5273 5274 5275 5276 5277 5278 5279 5280 5281 5282 5283 5284 5285 5286 5287 5288 5289 5290 5291 5292 5293 5294 5295 5296 5297 5298 5299 5300 5301 5302 5303 5304 5305 5306 5307 5308 5309 5310 5311 5312 5313 5314 5315 5316 5317 5318 5319 5320 5321 5322 5323 5324 5325 5326 5327 5328 5329 5330 5331 5332 5333 5334 5335 5336 5337 5338 5339 5340 5341 5342 5343 5344 5345 5346 5347 5348 5349 5350 5351 5352 5353 5354 5355 5356 5357 5358 5359 5360 5361 5362 5363 5364 5365 5366 5367 5368 5369 5370 5371 5372 5373 5374 5375 5376 5377 5378 5379 5380 5381 5382 5383 5384 5385 5386 5387 5388 5389 5390 5391 5392 5393 5394 5395 5396 5397 5398 5399 5400 5401 5402 5403 5404 5405 5406 5407 5408 5409 5410 5411 5412 5413 5414 5415 5416 5417 5418 5419 5420 5421 5422 5423 5424 5425 5426 5427 5428 5429 5430 5431 5432 5433 5434 5435 5436 5437 5438 5439 5440 5441 5442 5443 5444 5445 5446 5447 5448 5449 5450 5451 5452 5453 5454 5455 5456 5457 5458 5459 5460 5461 5462 5463 5464 5465 5466 5467 5468 5469 5470 5471 5472 5473 5474 5475 5476 5477 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487 5488 5489 5490 5491 5492 5493 5494 5495 5496 5497 5498 5499 5500 5501 5502 5503 5504 5505 5506 5507 5508 5509 5510 5511 5512 5513 5514 5515 5516 5517 5518 5519 5520 5521 5522 5523 5524 5525 5526 5527 5528 5529 5530 5531 5532 5533 5534 5535 5536 5537 5538 5539 5540 5541 5542 5543 5544 5545 5546 5547 5548 5549 5550 5551 5552 5553 5554 5555 5556 5557 5558 5559 5560 5561 5562 5563 5564 5565 5566 5567 5568 5569 5570 5571 5572 5573 5574 5575 5576 5577 5578 5579 5580 5581 5582 5583 5584 5585 5586 5587 5588 5589 5590 5591 5592 5593 5594 5595 5596 5597 5598 5599 5600 5601 5602 5603 5604 5605 5606 5607 5608 5609 5610 5611 5612 5613 5614 5615 5616 5617 5618 5619 5620 5621 5622 5623 5624 5625 5626 5627 5628 5629 5630 5631 5632 5633 5634 5635 5636 5637 5638 5639 5640 5641 5642 5643 5644 5645 5646 5647 5648 5649 5650 5651 5652 5653 5654 5655 5656 5657 5658 5659 5660 5661 5662 5663 5664 5665 5666 5667 5668 5669 5670 5671 5672 5673 5674 5675 5676 5677 5678 5679 5680 5681 5682 5683 5684 5685 5686 5687 5688 5689 5690 5691 5692 5693 5694 5695 5696 5697 5698 5699 5700 5701 5702 5703 5704 5705 5706 5707 5708 5709 5710 5711 5712 5713 5714 5715 5716 5717 5718 5719 5720 5721 5722 5723 5724 5725 5726 5727 5728 5729 5730 5731 5732 5733 5734 5735 5736 5737 5738 5739 5740 5741 5742 5743 5744 5745 5746 5747 5748 5749 5750 5751 5752 5753 5754 5755 5756 5757 5758 5759 5760 5761 5762 5763 5764 5765 5766 5767 5768 5769 5770 5771 5772 5773 5774 5775 5776 5777 5778 5779 5780 5781 5782 5783 5784 5785 5786 5787 5788 5789 5790 5791 5792 5793 5794 5795 5796 5797 5798 5799 5800 5801 5802 5803 5804 5805 5806 5807 5808 5809 5810 5811 5812 5813 5814 5815 5816 5817 5818 5819 5820 5821 5822 5823 5824 5825 5826 5827 5828 5829 5830 5831 5832 5833 5834 5835 5836 5837 5838 5839 5840 5841 5842 5843 5844 5845 5846 5847 5848 5849 5850 5851 5852 5853 5854 5855 5856 5857 5858 5859 5860 5861 5862 5863 5864 5865 5866 5867 5868 5869 5870 5871 5872 5873 5874 5875 5876 5877 5878 5879 5880 5881 5882 5883 5884 5885 5886 5887 5888 5889 5890 5891 5892 5893 5894 5895 5896 5897 5898 5899 5900 5901 5902 5903 5904 5905 5906 5907 5908 5909 5910 5911 5912 5913 5914 5915 5916 5917 5918 5919 5920 5921 5922 5923 5924 5925 5926 5927 5928 5929 5930 5931 5932 5933 5934 5935 5936 5937 5938 5939 5940 5941 5942 5943 5944 5945 5946 5947 5948 5949 5950 5951 5952 5953 5954 5955 5956 5957 5958 5959 5960 5961 5962 5963 5964 5965 5966 5967 5968 5969 5970 5971 5972 5973 5974 5975 5976 5977 5978 5979 5980 5981 5982 5983 5984 5985 5986 5987 5988 5989 5990 5991 5992 5993 5994 5995 5996 5997 5998 5999 6000 6001 6002 6003 6004 6005 6006 6007 6008 6009 6010 6011 6012 6013 6014 6015 6016 6017 6018 6019 6020 6021 6022 6023 6024 6025 6026 6027 6028 6029 6030 6031 6032 6033 6034 6035 6036 6037 6038 6039 6040 6041 6042 6043 6044 6045 6046 6047 6048 6049 6050 6051 6052 6053 6054 6055 6056 6057 6058 6059 6060 6061 6062 6063 6064 6065 6066 6067 6068 6069 6070 6071 6072 6073 6074 6075 6076 6077 6078 6079 6080 6081 6082 6083 6084 6085 6086 6087 6088 6089 6090 6091 6092 6093 6094 6095 6096 6097 6098 6099 6100 6101 6102 6103 6104 6105 6106 6107 6108 6109 6110 6111 6112 6113 6114 6115 6116 6117 6118 6119 6120 6121 6122 6123 6124 6125 6126 6127 6128 6129 6130 6131 6132 6133 6134 6135 6136 6137 6138 6139 6140 6141 6142 6143 6144 6145 6146 6147 6148 6149 6150 6151 6152 6153 6154 6155 6156 6157 6158 6159 6160 6161 6162 6163 6164 6165 6166 6167 6168 6169 6170 6171 6172 6173 6174 6175 6176 6177 6178 6179 6180 6181 6182 6183 6184 6185 6186 6187 6188 6189 6190 6191 6192 6193 6194 6195 6196 6197 6198 6199 6200 6201 6202 6203 6204 6205 6206 6207 6208 6209 6210 6211 6212 6213 6214 6215 6216 6217 6218 6219 6220 6221 6222 6223 6224 6225 6226 6227 6228 6229 6230 6231 6232 6233 6234 6235 6236 6237 6238 6239 6240 6241 6242 6243 6244 6245 6246 6247 6248 6249 6250 6251 6252 6253 6254 6255 6256 6257 6258 6259 6260 6261 6262 6263 6264 6265 6266 6267 6268 6269 6270 6271 6272 6273 6274 6275 6276 6277 6278 6279 6280 6281 6282 6283 6284 6285 6286 6287 6288 6289 6290 6291 6292 6293 6294 6295 6296 6297 6298 6299 6300 6301 6302 6303 6304 6305 6306 6307 6308 6309 6310 6311 6312 6313 6314 6315 6316 6317 6318 6319 6320 6321 6322 6323 6324 6325 6326 6327 6328 6329 6330 6331 6332 6333 6334 6335 6336 6337 6338 6339 6340 6341 6342 6343 6344 6345 6346 6347 6348 6349 6350 6351 6352 6353 6354 6355 6356 6357 6358 6359 6360 6361 6362 6363 6364 6365 6366 6367 6368 6369 6370 6371 6372 6373 6374 6375 6376 6377 6378 6379 6380 6381 6382 6383 6384 6385 6386 6387 6388 6389 6390 6391 6392 6393 6394 6395 6396 6397 6398 6399 6400 6401 6402 6403 6404 6405 6406 6407 6408 6409 6410 6411 6412 6413 6414 6415 6416 6417 6418 6419 6420 6421 6422 6423 6424 6425 6426 6427 6428 6429 6430 6431 6432 6433 6434 6435 6436 6437 6438 6439 6440 6441 6442 6443 6444 6445 6446 6447 6448 6449 6450 6451 6452 6453 6454 6455 6456 6457 6458 6459 6460 6461 6462 6463 6464 6465 6466 6467 6468 6469 6470 6471 6472 6473 6474 6475 6476 6477 6478 6479 6480 6481 6482 6483 6484 6485 6486 6487 6488 6489 6490 6491 6492 6493 6494 6495 6496 6497 6498 6499 6500 6501 6502 6503 6504 6505 6506 6507 6508 6509 6510 6511 6512 6513 6514 6515 6516 6517 6518 6519 6520 6521 6522 6523 6524 6525 6526 6527 6528 6529 6530 6531 6532 6533 6534 6535 6536 6537 6538 6539 6540 6541 6542 6543 6544 6545 6546 6547 6548 6549 6550 6551 6552 6553 6554 6555 6556 6557 6558 6559 6560 6561 6562 6563 6564 6565 6566 6567 6568 6569 6570 6571 6572 6573 6574 6575 6576 6577 6578 6579 6580 6581 6582 6583 6584 6585 6586 6587 6588 6589 6590 6591 6592 6593 6594 6595 6596 6597 6598 6599 6600 6601 6602 6603 6604 6605 6606 6607 6608 6609 6610 6611 6612 6613 6614 6615 6616 6617 6618 6619 6620 6621 6622 6623 6624 6625 6626 6627 6628 6629 6630 6631 6632 6633 6634 6635 6636 6637 6638 6639 6640 6641 6642 6643 6644 6645 6646 6647 6648 6649 6650 6651 6652 6653 6654 6655 6656 6657 6658 6659 6660 6661 6662 6663 6664 6665 6666 6667 6668 6669 6670 6671 6672 6673 6674 6675 6676 6677 6678 6679 6680 6681 6682 6683 6684 6685 6686 6687 6688 6689 6690 6691 6692 6693 6694 6695 6696 6697 6698 6699 6700 6701 6702 6703 6704 6705 6706 6707 6708 6709 6710 | /*
* Portions Copyright 2008, 2009 VMware, Inc.
*/
/*
* Adaptec ADP94xx SAS HBA device driver for Linux.
*
* Written by : David Chaw <david_chaw@adaptec.com>
* Modified by : Naveen Chandrasekaran <naveen_chandrasekaran@adaptec.com>
*
* Copyright (c) 2004 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/razor/linux/src/adp94xx_hwi.c#161 $
*
*/
#include "adp94xx_osm.h"
#include "adp94xx_inline.h"
#if KDB_ENABLE
#include "linux/kdb.h"
#endif
/* Local functions' prototypes */
static u_int asd_sglist_allocsize(struct asd_softc *asd);
static int asd_hwi_init_scbdata(struct asd_softc *asd);
static int asd_hwi_reset_hw(struct asd_softc *asd);
static void asd_hwi_exit_hw(struct asd_softc *asd);
static void asd_hwi_setup_sw_bar(struct asd_softc *asd);
static int asd_hwi_init_phys(struct asd_softc *asd);
static int asd_hwi_init_ports(struct asd_softc *asd);
static void asd_hwi_alloc_scbs(struct asd_softc *asd);
static int asd_hwi_init_sequencers(struct asd_softc *asd);
static void asd_hwi_process_dl(struct asd_softc *asd);
static void asd_hwi_build_id_frame(struct asd_phy *phy);
static void asd_hwi_build_smp_phy_req(struct asd_port *port, int req_type,
int phy_id, int ctx);
/* SCB completion post routines. */
static void asd_hwi_process_phy_comp(struct asd_softc *asd,
struct scb *scb,
struct control_phy_sb *cntrl_phy);
static void asd_hwi_process_edb(struct asd_softc *asd,
struct asd_done_list *dl_entry);
static void asd_hwi_process_prim_event(struct asd_softc *asd,
struct asd_phy *phy,
u_int reg_addr, u_int reg_content);
static void asd_hwi_process_phy_event(struct asd_softc *asd,
struct asd_phy *phy, u_int oob_status,
u_int oob_mode);
static void asd_hwi_process_timer_event(struct asd_softc *asd,
struct asd_phy *phy, uint8_t error);
static void asd_hwi_handle_link_rst_err(struct asd_softc *asd,
struct asd_phy *phy);
static void asd_hwi_process_req_task(struct asd_softc *asd,
uint8_t req_type, uint16_t index);
/* Error Handling routines. */
static void asd_scb_eh_timeout(u_long arg);
static void asd_hwi_abort_scb(struct asd_softc *asd,
struct scb *scb_to_abort, struct scb *scb);
static void asd_hwi_reset_lu(struct asd_softc *asd,
struct scb *scb_to_reset, struct scb *scb);
static void asd_hwi_reset_device(struct asd_softc *asd,
struct scb *scb_to_reset, struct scb *scb);
static void asd_hwi_resume_sendq(struct asd_softc *asd,
struct scb *scb_to_reset, struct scb *scb);
static void asd_hwi_resume_sendq_done(struct asd_softc *asd, struct scb *scb,
struct asd_done_list *dl);
static void asd_hwi_reset_end_device(struct asd_softc *asd,
struct scb *scb);
static void asd_hwi_reset_exp_device(struct asd_softc *asd,
struct scb *scb);
static void asd_hwi_report_phy_err_log(struct asd_softc *asd,
struct scb *scb);
static void asd_hwi_dump_phy_err_log(struct asd_port *port,
struct scb *scb);
static void asd_hwi_reset_port(struct asd_softc *asd,
struct scb *scb_to_reset, struct scb *scb);
static asd_scb_post_t asd_hwi_abort_scb_done;
static asd_scb_post_t asd_hwi_reset_lu_done;
static asd_scb_post_t asd_hwi_reset_device_done;
static asd_scb_post_t asd_hwi_reset_end_device_done;
static asd_scb_post_t asd_hwi_reset_exp_device_done;
static asd_scb_post_t asd_hwi_reset_port_done;
static asd_scb_eh_post_t asd_hwi_req_task_done;
/* Function prototypes for NVRAM access utilites. */
#if NVRAM_SUPPORT
static int asd_hwi_poll_nvram(struct asd_softc *asd);
static int asd_hwi_chk_write_status(struct asd_softc *asd,
uint32_t sector_addr,
uint8_t erase_flag);
static int asd_hwi_reset_nvram(struct asd_softc *asd);
int asd_hwi_search_nv_cookie(struct asd_softc *asd,
uint32_t *addr,
struct asd_flash_dir_layout *pflash_dir_buf);
static int asd_hwi_erase_nv_sector(struct asd_softc *asd,
uint32_t sector_addr);
static int asd_hwi_verify_nv_checksum(struct asd_softc *asd,
u_int segment_id,
uint8_t *segment_ptr,
u_int bytes_to_read);
static int asd_hwi_get_nv_config(struct asd_softc *asd);
static int asd_hwi_search_nv_id(struct asd_softc *asd,
u_int setting_id,
void *dest, u_int *src_offset,
u_int bytes_to_read);
static int asd_hwi_get_nv_phy_settings(struct asd_softc *asd);
static int asd_hwi_map_lrate_from_sas(u_int sas_link_rate,
u_int *asd_link_rate);
static int asd_hwi_get_nv_manuf_seg(struct asd_softc *asd, void *dest,
uint32_t bytes_to_read,
uint32_t *src_offset,
uint16_t signature);
static void asd_hwi_get_nv_phy_params(struct asd_softc *asd);
static int asd_hwi_check_flash(struct asd_softc *asd);
#endif /* NVRAM_SUPPORT */
/* OCM access routines */
static int asd_hwi_get_ocm_info(struct asd_softc *asd);
static int asd_hwi_get_ocm_entry(struct asd_softc *asd,
uint32_t entry_type,
struct asd_ocm_entry_format *pocm_de,
uint32_t *src_offset);
static int asd_hwi_read_ocm_seg(struct asd_softc *asd, void *dest,
uint32_t src_offset, u_int bytes_to_read,
u_int *bytes_read);
static int asd_hwi_set_speed_mask(u_int asd_link_rate,
uint8_t *asd_speed_mask);
#if SAS_COMSTOCK_SUPPORT
static void asd_hwi_get_rtl_ver(struct asd_softc *asd);
#endif
#ifdef ASD_TEST
static void asd_hwi_dump_phy(struct asd_phy *phy);
static void asd_hwi_dump_phy_id_addr(struct asd_phy *phy);
#endif
/*
* Function:
* asd_sglist_allocsize
*
* Description:
* Calculate the optimum S/G List allocation size. S/G elements used
* for a given transaction must be physically contiguous. Assume the
* OS will allocate full pages to us, so it doesn't make sense to request
* less than a page.
*/
static u_int
asd_sglist_allocsize(struct asd_softc *asd)
{
uint32_t sg_list_increment;
uint32_t sg_list_size;
uint32_t max_list_size;
uint32_t best_list_size;
/* Start out with the minimum required for ASD_NSEG. */
sg_list_increment = asd_sglist_size(asd);
sg_list_size = sg_list_increment;
/* Get us as close as possible to a page in size. */
while ((sg_list_size + sg_list_increment) <= PAGE_SIZE)
sg_list_size += sg_list_increment;
/*
* Try to reduce the amount of wastage by allocating
* multiple pages.
*/
best_list_size = sg_list_size;
max_list_size = roundup(sg_list_increment, PAGE_SIZE);
if (max_list_size < 4 * PAGE_SIZE)
max_list_size = 4 * PAGE_SIZE;
if (max_list_size > (ASD_MAX_ALLOCATED_SCBS * sg_list_increment))
max_list_size = (ASD_MAX_ALLOCATED_SCBS * sg_list_increment);
while ((sg_list_size + sg_list_increment) <= max_list_size
&& (sg_list_size % PAGE_SIZE) != 0) {
uint32_t new_mod;
uint32_t best_mod;
sg_list_size += sg_list_increment;
new_mod = sg_list_size % PAGE_SIZE;
best_mod = best_list_size % PAGE_SIZE;
if (new_mod > best_mod || new_mod == 0) {
best_list_size = sg_list_size;
}
}
return (best_list_size);
}
static int
asd_hwi_init_scbdata(struct asd_softc *asd)
{
struct scb *scb;
u_int scb_cnt;
int loop_cnt;
asd->scbindex = asd_alloc_mem(
asd->hw_profile.max_scbs * sizeof(struct scb *),
GFP_ATOMIC);
if (asd->scbindex == NULL)
return (-ENOMEM);
memset(asd->scbindex, 0x0,
asd->hw_profile.max_scbs * sizeof(struct scb *));
asd->init_level++;
asd->qinfifo = asd_alloc_mem(
asd->hw_profile.max_scbs * sizeof(*asd->qinfifo),
GFP_ATOMIC);
if (asd->qinfifo == NULL) {
asd_free_mem(asd->scbindex);
return (-ENOMEM);
}
asd->init_level++;
/*
* Create our DMA tags. These tags define the kinds of device
* accessible memory allocations and memory mappings we will
* need to perform during normal operation.
*/
/* DMA tag for our hardware scb structures */
if (asd_dma_tag_create(asd, 1, PAGE_SIZE, GFP_ATOMIC,
&asd->hscb_dmat) != 0) {
asd_hwi_exit_hw(asd);
goto error_exit;
}
asd->init_level++;
/* DMA tag for our S/G structures. */
if (asd_dma_tag_create(asd, 8, asd_sglist_allocsize(asd),
GFP_ATOMIC, &asd->sg_dmat) != 0) {
asd_hwi_exit_hw(asd);
goto error_exit;
}
asd->init_level++;
/* Perform initial SCB allocation */
asd_hwi_alloc_scbs(asd);
if (asd->numscbs == 0) {
asd_print("%s: Unable to allocate initial scbs\n",
asd_name(asd));
asd_hwi_exit_hw(asd);
goto error_exit;
}
/*
* Make sure we are able to allocate more than the reserved
* SCB requirements.
*/
loop_cnt = 0;
while (asd->numscbs < ASD_RSVD_SCBS) {
/*
* Allocate SCB until we have more than the reserved SCBs
* requirement.
*/
asd_hwi_alloc_scbs(asd);
if (++loop_cnt > 4)
break;
}
if (asd->numscbs < ASD_RSVD_SCBS) {
asd_log(ASD_DBG_ERROR, "Failed to allocate reserved pool of "
"SCBs.\n");
asd_hwi_exit_hw(asd);
goto error_exit;
}
scb_cnt = 0;
/* Save certain amount of SCBs as reserved. */
while (!list_empty(&asd->free_scbs)) {
scb = list_entry(asd->free_scbs.next, struct scb, hwi_links);
list_del(&scb->hwi_links);
list_add_tail(&scb->hwi_links, &asd->rsvd_scbs);
if (++scb_cnt > ASD_RSVD_SCBS)
break;
}
#ifdef EXTENDED_SCB
{
/* allocate memory for extended scb*/
/* reserved 128 byte more for 128 bytes alignment*/
if (asd_alloc_dma_mem(asd, SCB_SIZE * (ASD_EXTENDED_SCB_NUMBER+1),
(void **)&asd->ext_scb_map.vaddr,
&asd->ext_scb_map.busaddr,
&asd->ext_scb_dmat,
&asd->ext_scb_map) != 0) {
asd_hwi_exit_hw(asd);
goto error_exit;
}
#ifdef ASD_DEBUG
asd_print("EXTENDED_SCB is allocated\n");
#endif
}
#endif
return (0);
error_exit:
return (-ENOMEM);
}
/*
* Function:
* asd_alloc_softc()
*
* Description:
* Allocate a softc structure and setup necessary fields.
*/
struct asd_softc *
asd_alloc_softc(asd_dev_t dev)
{
struct asd_softc *asd;
asd = asd_alloc_mem(sizeof(*asd), GFP_KERNEL);
if (asd == NULL) {
asd_log(ASD_DBG_ERROR, "Unable to alloc softc.\n");
return (NULL);
}
memset(asd, 0x0, sizeof(*asd));
INIT_LIST_HEAD(&asd->rsvd_scbs);
INIT_LIST_HEAD(&asd->free_scbs);
INIT_LIST_HEAD(&asd->pending_scbs);
INIT_LIST_HEAD(&asd->timedout_scbs);
INIT_LIST_HEAD(&asd->empty_scbs);
INIT_LIST_HEAD(&asd->hscb_maps);
INIT_LIST_HEAD(&asd->sg_maps);
asd->dev = dev;
if (asd_platform_alloc(asd) != 0) {
asd_free_softc(asd);
asd = NULL;
}
return (asd);
}
/*
* Function:
* asd_free_softc()
*
* Description:
* Free the host structure and any memory allocated for its member fields.
* Also perform cleanup for module unloading purpose.
*/
void
asd_free_softc(struct asd_softc *asd)
{
asd_platform_free(asd);
/* Free any internal data structures */
asd_hwi_exit_hw(asd);
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) && \
LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
if (asd->dev != NULL)
asd->dev->driver = NULL;
#endif
asd_free_mem(asd);
}
void
asd_intr_enable(struct asd_softc *asd, int enable)
{
asd_write_dword(asd, CHIMINTEN, enable ? SET_CHIMINTEN : 0);
}
static int
asd_hwi_reset_hw(struct asd_softc *asd)
{
u_int i;
#define ASD_RESET_DELAY 10
#define ASD_RESET_LOOP_COUNT (1 * 1000000 / ASD_RESET_DELAY)
for (i = 0 ; i < 4 ; i++) {
asd_write_dword(asd, COMBIST, HARDRST);
}
for (i = 0; i < ASD_RESET_LOOP_COUNT; i++) {
asd_delay(ASD_RESET_DELAY);
if (asd_read_dword(asd, CHIMINT) & HARDRSTDET)
break;
}
if (i >= ASD_RESET_LOOP_COUNT) {
asd_log(ASD_DBG_ERROR, "Chip reset failed.\n");
return (-EIO);
}
return (0);
}
#ifdef ASD_DEBUG
typedef struct pcic_regs {
uint8_t name[32];
uint16_t offset;
} pcic_regs_t;
static pcic_regs_t PCICREG[] =
{
{"DEVICE-VENDOR" ,0x00},
{"COMMAND-STATUS" ,0x04},
{"DEVREV-CLASS" ,0x08},
{"SUB_VENDOR-ID" ,0x2c},
{"XBAR" ,0x30},
{"PCIX_CAP-CMD" ,0x42},
{"PCIX_STATUS" ,0x44},
{"MBAR1" ,0x6c},
{"MBAR0-WA" ,0x70},
{"MBAR0-WB" ,0x74},
{"MBAR0-WC" ,0x78},
{"MBARKEY" ,0x7c},
{"HREX_CTL" ,0x80},
{"HREX_STATUS" ,0x84},
{"RBI_CTL" ,0x88},
{"RBI_STATUS" ,0x8c},
{"CF_ADR_L" ,0x90},
{"CF_ADR_H" ,0x94},
{"DF_ADR_L" ,0x98},
{"DF_ADR_H" ,0x9c},
{"HSTPCIX_CTL" ,0xa0},
{"HSTPCIX_STATUS" ,0xa4},
{"FLSH_BAR" ,0xb8},
{"", 0 } /* Last entry should be NULL. */
};
void DumpPCI(struct asd_softc *asd)
{
uint32_t regvalue;
uint32_t i;
i=0;
asd_print("**PCI REG DUMP********************\n");
while(PCICREG[i].name[0]!=0)
{
regvalue = asd_pcic_read_dword(asd, PCICREG[i].offset);
asd_print(" %s (0x%x) : 0x%x\n", PCICREG[i].name, PCICREG[i].offset, regvalue);
i++;
}
asd_print("**********************************\n");
}
#endif
/*
* Function:
* asd_hwi_init_hw()
*
* Description:
* Perform controller specific initialization.
*/
int
asd_hwi_init_hw(struct asd_softc *asd)
{
union hardware_scb *hscb;
struct scb *scb;
uint8_t *next_vaddr;
dma_addr_t next_baddr;
dma_addr_t edb_baddr;
size_t driver_data_size;
size_t dl_size;
uint8_t enabled_phys;
u_int num_edbs;
u_int num_escbs;
u_int i;
int error;
u_long flags;
/* Setup the Sliding Window BAR. */
asd_hwi_setup_sw_bar(asd);
#if SAS_COMSTOCK_SUPPORT
/*
* Retrieve the RTL number. The RTL Number will be used to decide which
* sequencer version to use.
*/
asd_hwi_get_rtl_ver(asd);
/* No support for COMSTOCK RTL less than version 14. */
if (asd->hw_profile.rev_id < COMSTOCK_LATEST_RTL)
return (-ENODEV);
#endif
/* Allocate SCB data */
if (asd_hwi_init_scbdata(asd) != 0)
return (-ENOMEM);
/*
* DMA tag for our done_list, empty buffers, empty hardware SCBs,
* and sentinel hardware SCB. These are data host memory structures
* the controller must be able to access.
*
* The number of elements in our done list must be a powerof2
* greater than or equal to 4 that is large enough to guarantee
* it cannot overflow. Since each done list entry is associated
* with either an empty data buffer or an SCB, add the counts for
* these two objects together and roundup to the next power of 2.
* To ensure our sequencers don't stall, we need two empty buffers
* per sequencer (1 sequencer per-phy plus central seq). We round
* this up to a multiple of the number of EDBs that we can fit in
* a single empty SCB.
*/
num_edbs = roundup(2 * (asd->hw_profile.max_phys + 1),
ASD_MAX_EDBS_PER_SCB);
/*
* At minimum, allocate 2 empty SCBs so that the sequencers
* always have empty buffers while we are trying to queue more.
*/
num_edbs = MAX(num_edbs, 2 * ASD_MAX_EDBS_PER_SCB);
num_escbs = num_edbs / ASD_MAX_EDBS_PER_SCB;
dl_size = asd->hw_profile.max_scbs + num_edbs;
dl_size = roundup_pow2(dl_size);
asd->dl_wrap_mask = dl_size - 1;
dl_size *= sizeof(*asd->done_list);
driver_data_size = dl_size + (ASD_SCB_SIZE) /* for sentinel */ +
+ (num_escbs * ASD_SCB_SIZE)
+ (num_edbs * sizeof(union edb));
if (asd_dma_tag_create(asd, 8, driver_data_size, GFP_ATOMIC,
&asd->shared_data_dmat) != 0) {
asd_hwi_exit_hw(asd);
return (-ENOMEM);
}
asd->init_level++;
/* Allocation of driver data */
if (asd_dmamem_alloc(asd, asd->shared_data_dmat,
(void **)&asd->shared_data_map.vaddr, GFP_ATOMIC,
&asd->shared_data_map.dmamap,
&asd->shared_data_map.busaddr) != 0) {
asd_hwi_exit_hw(asd);
return (-ENOMEM);
}
asd->init_level++;
/*
* Distribute the memory.
*/
memset(asd->shared_data_map.vaddr, 0, driver_data_size);
asd->done_list = (struct asd_done_list *)asd->shared_data_map.vaddr;
asd->dl_valid = ASD_QDONE_PASS_DEF;
next_vaddr = asd->shared_data_map.vaddr + dl_size;
next_baddr = asd->shared_data_map.busaddr + dl_size;
/*
* We need one SCB to serve as the "next SCB". Since the
* tag identifier in this SCB will never be used, there is
* no point in using a valid HSCB tag from an SCB pulled from
* the standard free pool. So, we allocate this "sentinel"
* specially from the DMA safe memory chunk.
*/
asd->next_queued_hscb = (union hardware_scb *)next_vaddr;
asd->next_queued_hscb_map = &asd->shared_data_map;
asd->next_queued_hscb_busaddr = asd_htole64(next_baddr);
next_vaddr += ASD_SCB_SIZE;
next_baddr += ASD_SCB_SIZE;
/*
* Since Empty SCBs do not require scatter gather lists
* we also allocate them outside of asd_alloc_scbs().
*/
hscb = asd->next_queued_hscb + 1;
edb_baddr = next_baddr + (num_escbs * ASD_SCB_SIZE);
for (i = 0; i < num_escbs; i++, hscb++, next_baddr += ASD_SCB_SIZE) {
int j;
/*
* Allocate ESCBs.
*/
scb = asd_alloc_mem(sizeof(*scb), GFP_ATOMIC);
if (scb == NULL) {
error = -ENOMEM;
goto exit;
}
memset(scb, 0, sizeof(*scb));
INIT_LIST_HEAD(&scb->hwi_links);
INIT_LIST_HEAD(&scb->owner_links);
scb->hscb = hscb;
scb->hscb_busaddr = asd_htole64(next_baddr);
scb->softc = asd;
scb->hscb_map = &asd->shared_data_map;
hscb->header.index = asd_htole16(asd->numscbs);
hscb->header.opcode = SCB_EMPTY_BUFFER;
asd->scbindex[asd->numscbs++] = scb;
hscb->empty_scb.num_valid_elems = ASD_MAX_EDBS_PER_SCB;
for (j = 0; j < ASD_MAX_EDBS_PER_SCB; j++) {
hscb->empty_scb.buf_elem[j].busaddr =
asd_htole64(edb_baddr);
hscb->empty_scb.buf_elem[j].buffer_size =
asd_htole32(sizeof(union edb));
hscb->empty_scb.buf_elem[j].elem_valid_ds =
ELEM_BUFFER_VALID;
edb_baddr += sizeof(union edb);
}
list_add(&scb->hwi_links, &asd->empty_scbs);
}
asd->init_level++;
/* Allocate Free DDB bitmap. */
asd->ddb_bitmap_size = roundup(asd->hw_profile.max_ddbs, BITS_PER_LONG);
asd->ddb_bitmap_size /= BITS_PER_LONG;
asd->free_ddb_bitmap = asd_alloc_mem((asd->ddb_bitmap_size *
sizeof(u_long)), GFP_ATOMIC);
if (asd->free_ddb_bitmap == NULL)
return (-ENOMEM);
memset(asd->free_ddb_bitmap, 0, sizeof(u_long) * asd->ddb_bitmap_size);
/*
* DDB site 0 and 1 are reserved for the firmware for internal use.
*/
asd->free_ddb_bitmap[0] |= (u_long)(3UL<<0);
//JD
#ifdef ASD_DEBUG
asd_log(ASD_DBG_INFO, "asd->free_ddb_bitmap ptr 0x%x\n",asd->free_ddb_bitmap);
asd_print("%llx %llx\n",(u64)asd->free_ddb_bitmap[0], (u64)asd->free_ddb_bitmap[1]);
#endif
asd->init_level++;
#ifdef ASD_DEBUG
asd_log(ASD_DBG_INFO, "After initial BAR Setting\n");
DumpPCI(asd);
#endif
/* Retrieve OCM information */
if (asd_hwi_get_ocm_info(asd)) {
asd_log(ASD_DBG_ERROR, "Failed to retrieve OCM info.\n");
/* TBD: return -1; ? */
}
#ifdef ASD_DEBUG
asd_log(ASD_DBG_INFO, "After asd_hwi_get_ocm_info\n");
DumpPCI(asd);
#endif
#if NVRAM_SUPPORT
/*
* Retrieves controller NVRAM setting.
*/
error = asd_hwi_get_nv_config(asd);
if (error != 0) {
asd_log(ASD_DBG_ERROR, "Failed to retrieve NVRAM config.\n");
}
#ifdef ASD_DEBUG
asd_log(ASD_DBG_INFO, "After asd_hwi_get_nv_config\n");
DumpPCI(asd);
#endif
#endif
/* Initialize the phy and port to default settings. */
error = asd_hwi_init_phys(asd);
if (error != 0) {
asd_log(ASD_DBG_ERROR, "Failed to init the phys.\n");
asd_hwi_exit_hw(asd);
goto exit;
}
error = asd_hwi_init_ports(asd);
if (error != 0) {
asd_log(ASD_DBG_ERROR, "Failed to init the ports.\n");
asd_hwi_exit_hw(asd);
goto exit;
}
if (asd_hwi_reset_hw(asd) != 0) {
asd_log(ASD_DBG_ERROR, "Failed to perform Chip reset.\n");
asd_hwi_exit_hw(asd);
goto exit;
}
asd_write_dword(asd, CHIMINT, PORRSTDET|HARDRSTDET);
/*
* Reset the producer and consumer index to reflect
* no outstanding SCBs.
*/
asd->qinfifonext = (asd_read_dword(asd, SCBPRO) & SCBCONS_MASK) >> 16;
asd_write_dword(asd, SCBPRO, asd->qinfifonext);
asd->qinfifonext = asd_read_word(asd, SCBPRO+2);
/* Disable the Host interrupts. */
asd_write_dword(asd, CHIMINTEN, RST_CHIMINTEN);
/* Initialize and setup the CSEQ and LSEQ. */
error = asd_hwi_init_sequencers(asd);
if (error != 0) {
asd_log(ASD_DBG_ERROR, "Failed to init the SEQ.\n");
goto exit;
}
/* CSEQ should be ready to run. Start the CSEQ. */
error = asd_hwi_start_cseq(asd);
if (error != 0) {
asd_log(ASD_DBG_ERROR, "Failed to start the CSEQ.\n");
goto exit;
}
/* Start the LSEQ(s). */
i = 0;
enabled_phys = asd->hw_profile.enabled_phys;
while (enabled_phys != 0) {
for ( ; i < asd->hw_profile.max_phys; i++) {
if (enabled_phys & (1U << i)) {
enabled_phys &= ~(1U << i);
break;
}
}
error = asd_hwi_start_lseq(asd, i);
if (error != 0) {
asd_log(ASD_DBG_ERROR,
"Failed to start LSEQ %d.\n", i);
goto exit;
}
}
asd_lock(asd, &flags);
/*
* Post all of our empty scbs to the central sequencer.
*/
list_for_each_entry(scb, &asd->empty_scbs, hwi_links) {
asd_hwi_post_scb(asd, scb);
}
asd_unlock(asd, &flags);
/* Enabled all the phys. */
i = 0;
enabled_phys = asd->hw_profile.enabled_phys;
while (enabled_phys != 0) {
for ( ; i < asd->hw_profile.max_phys; i++) {
if (enabled_phys & (1 << i)) {
enabled_phys &= ~(1 << i);
break;
}
}
error = asd_hwi_enable_phy(asd, asd->phy_list[i]);
if (error != 0) {
/*
* TODO: This shouldn't happen.
* Need more thought on how to proceed.
*/
asd_log(ASD_DBG_ERROR, "Failed to enable phy %d.\n", i);
break;
}
}
exit:
#ifdef ASD_DEBUG
asd->debug_flag=0;
#endif
return (error);
}
#if SAS_COMSTOCK_SUPPORT
/*
* Function:
* asd_hwi_get_rtl_ver()
*
* Description:
* Retrive the COMSTOCK rtl version.
*/
static void
asd_hwi_get_rtl_ver(struct asd_softc *asd)
{
uint32_t exsi_base_addr;
uint32_t reg_addr;
uint8_t reg_data;
exsi_base_addr = EXSI_REG_BASE_ADR + XREGADDR;
reg_addr = asd_hwi_swb_read_dword(asd, exsi_base_addr);
asd_hwi_swb_write_dword(asd, exsi_base_addr, (uint32_t)
(reg_addr & ~(XRADDRINCEN | XREGADD_MASK)));
reg_data = asd_hwi_swb_read_byte(asd, EXSI_REG_BASE_ADR + XREGDATAR);
asd_hwi_swb_write_dword(asd, exsi_base_addr, reg_addr);
asd->hw_profile.rev_id = reg_data;
}
#endif /* SAS_COMSTOCK_SUPPORT */
/*
* Function:
* asd_hwi_exit_hw()
*
* Description:
* Perform controller specific cleanup.
*/
static void
asd_hwi_exit_hw(struct asd_softc *asd)
{
struct scb *scb;
struct map_node *map;
struct asd_phy *phy;
struct asd_port *port;
u_int i;
/*
* Reset the chip so that the sequencers do not
* attempt to DMA data into buffers we are about
* to remove or issue further interrupts.
*/
/* TBRV: This seems to fail all the time. */
//asd_hwi_reset_hw(asd);
/* Clean up the phy structures */
for (i = 0; i < asd->hw_profile.max_phys; i++) {
if (asd->phy_list[i] != NULL) {
phy = asd->phy_list[i];
/* Free the ID ADDR Frame buffer. */
asd_free_dma_mem(asd, phy->id_addr_dmat,
&phy->id_addr_map);
asd_free_mem(asd->phy_list[i]);
}
}
/* Clean up the port structures */
for (i = 0; i < asd->hw_profile.max_ports; i++) {
if (asd->port_list[i] != NULL) {
port = asd->port_list[i];
/*
* Free SMP Request Frame buffer.
*/
asd_free_dma_mem(asd,
port->dc.smp_req_dmat,
&port->dc.smp_req_map);
/*
* Free SMP Response Frame buffer.
*/
asd_free_dma_mem(asd,
port->dc.smp_resp_dmat,
&port->dc.smp_resp_map);
asd_free_mem(asd->port_list[i]);
}
}
/* Free up the SCBs */
while (!list_empty(&asd->pending_scbs)) {
scb = list_entry(asd->pending_scbs.next, struct scb, hwi_links);
asd_log(ASD_DBG_INFO, "freeing pending scb 0x%x scb->hwi_links 0x%p",scb, &scb->hwi_links);
list_del(&scb->hwi_links);
asd_free_scb_platform_data(asd, scb->platform_data);
asd_free_mem(scb);
}
while (!list_empty(&asd->rsvd_scbs)) {
scb = list_entry(asd->rsvd_scbs.next, struct scb, hwi_links);
list_del(&scb->hwi_links);
asd_free_scb_platform_data(asd, scb->platform_data);
asd_free_mem(scb);
}
while (!list_empty(&asd->free_scbs)) {
scb = list_entry(asd->free_scbs.next, struct scb, hwi_links);
list_del(&scb->hwi_links);
asd_free_scb_platform_data(asd, scb->platform_data);
asd_free_mem(scb);
}
while (!list_empty(&asd->empty_scbs)) {
/*
* Empties have no OSM data.
*/
scb = list_entry(asd->empty_scbs.next, struct scb, hwi_links);
list_del(&scb->hwi_links);
asd_free_mem(scb);
}
/* Free up DMA safe memory shared with the controller */
while (!list_empty(&asd->hscb_maps)) {
map = list_entry(asd->hscb_maps.next, struct map_node, links);
list_del(&map->links);
asd_dmamem_free(asd, asd->hscb_dmat, map->vaddr, map->dmamap);
asd_free_mem(map);
}
while (!list_empty(&asd->sg_maps)) {
map = list_entry(asd->sg_maps.next, struct map_node, links);
list_del(&map->links);
asd_dmamem_free(asd, asd->sg_dmat, map->vaddr, map->dmamap);
asd_free_mem(map);
}
switch (asd->init_level) {
default:
case 7:
asd_free_mem(asd->free_ddb_bitmap);
/* FALLTHROUGH */
case 6:
asd_dmamem_free(asd, asd->shared_data_dmat,
asd->shared_data_map.vaddr,
asd->shared_data_map.dmamap);
/* FALLTHROUGH */
case 5:
asd_dma_tag_destroy(asd, asd->shared_data_dmat);
/* FALLTHROUGH */
case 4:
#ifdef EXTENDED_SCB
{
/* free memory for extended scb*/
asd_free_dma_mem(asd, asd->ext_scb_dmat, &asd->ext_scb_map);
#ifdef ASD_DEBUG
asd_print("EXTENDED_SCB is freed\n");
#endif
}
#endif
asd_dma_tag_destroy(asd, asd->sg_dmat);
/* FALLTHROUGH */
case 3:
asd_dma_tag_destroy(asd, asd->hscb_dmat);
/* FALLTHROUGH */
case 2:
asd_free_mem(asd->qinfifo);
/* FALLTHROUGH */
case 1:
asd_free_mem(asd->scbindex);
/* FALLTHROUGH */
case 0:
break;
}
}
/*
* Function:
* asd_hwi_setup_sw_bar()
*
* Description:
* Setup the location of internal space where the Sliding Window will
* point to.
*/
static void
asd_hwi_setup_sw_bar(struct asd_softc *asd)
{
/* Setup Sliding Window A and B to point to CHIM_REG_BASE_ADR. */
asd_write_dword(asd, PCIC_BASEA, CHIM_REG_BASE_ADR);
asd_write_dword(asd, PCIC_BASEB, CHIM_REG_BASE_ADR);
asd->io_handle[0]->swb_base = (uint32_t) CHIM_REG_BASE_ADR;
}
/*
* Function:
* asd_hwi_init_phys()
*
* Description:
* Alllocate phy structures and intialize them to default settings.
*/
static int
asd_hwi_init_phys(struct asd_softc *asd)
{
struct asd_phy *phy;
u_int phy_id;
for (phy_id = 0; phy_id < asd->hw_profile.max_phys; phy_id++) {
phy = asd_alloc_mem(sizeof(*phy), GFP_KERNEL);
if (phy == NULL) {
asd_log(ASD_DBG_ERROR," Alloc Phy failed.\n");
return (-ENOMEM);
}
memset(phy, 0x0, sizeof(*phy));
/* Fill in the default settings. */
phy->id = phy_id;
phy->max_link_rate = SAS_30GBPS_RATE;
phy->min_link_rate = SAS_15GBPS_RATE;
/*
* Set the phy attributes to support SSP, SMP and STP
* initiator mode. Target mode is not supported.
*/
phy->attr = (ASD_SSP_INITIATOR | ASD_SMP_INITIATOR |
ASD_STP_INITIATOR);
/*
* By default, use the adapter WWN as the SAS address for
* the phy.
*/
memcpy(phy->sas_addr, asd->hw_profile.wwn, SAS_ADDR_LEN);
/* Allocate buffer for IDENTIFY ADDRESS frame. */
if (asd_dma_tag_create(asd, 8, sizeof(struct sas_id_addr),
GFP_ATOMIC, &phy->id_addr_dmat) != 0)
return (-ENOMEM);
if (asd_dmamem_alloc(asd, phy->id_addr_dmat,
(void **) &phy->id_addr_map.vaddr,
GFP_ATOMIC,
&phy->id_addr_map.dmamap,
&phy->id_addr_map.busaddr) != 0) {
asd_dma_tag_destroy(asd, phy->id_addr_dmat);
return (-ENOMEM);
}
INIT_LIST_HEAD(&phy->pending_scbs);
phy->state = ASD_PHY_UNUSED;
phy->src_port = NULL;
phy->softc = (void *) asd;
INIT_LIST_HEAD(&phy->links);
phy->pat_gen = 0;
asd->phy_list[phy_id] = phy;
}
asd_hwi_get_nv_phy_settings(asd);
asd_hwi_get_nv_phy_params(asd);
return (0);
}
/*
* Function:
* asd_hwi_init_ports()
*
* Description:
* Alllocate port structures and intialize them to default settings.
*/
static int
asd_hwi_init_ports(struct asd_softc *asd)
{
struct asd_port *port;
u_char i;
for (i = 0; i < asd->hw_profile.max_ports; i++) {
port = asd_alloc_mem(sizeof(*port), GFP_ATOMIC);
if (port == NULL) {
asd_log(ASD_DBG_ERROR," Alloc Port failed.\n");
return (-ENOMEM);
}
memset(port, 0x0, sizeof(*port));
INIT_LIST_HEAD(&port->phys_attached);
INIT_LIST_HEAD(&port->targets);
INIT_LIST_HEAD(&port->targets_to_validate);
if (asd_alloc_dma_mem(asd, sizeof(struct SMPRequest),
(void **)&port->dc.SMPRequestFrame,
&port->dc.SMPRequestBusAddr,
&port->dc.smp_req_dmat,
&port->dc.smp_req_map) != 0) {
return (-ENOMEM);
}
if (asd_alloc_dma_mem(asd, sizeof(struct SMPResponse),
(void **)&port->dc.SMPResponseFrame,
&port->dc.SMPResponseBusAddr,
&port->dc.smp_resp_dmat,
&port->dc.smp_resp_map) != 0) {
/*
* If we get get the response, free the request.
*/
asd_free_dma_mem(asd,
port->dc.smp_req_dmat,
&port->dc.smp_req_map);
return (-ENOMEM);
}
/*
* The SASInfoFrame includes the length of the list as the
* first element.
*/
port->dc.sas_info_len = MAX(
(ASD_MAX_LUNS + 1) * sizeof(uint64_t),
PRODUCT_SERIAL_NUMBER_LEN);
if (asd_alloc_dma_mem(asd,
port->dc.sas_info_len,
(void **)&port->dc.SASInfoFrame,
&port->dc.SASInfoBusAddr,
&port->dc.sas_info_dmat,
&port->dc.sas_info_map) != 0) {
/*
* If we get get the report luns ...
*/
asd_free_dma_mem(asd,
port->dc.smp_req_dmat,
&port->dc.smp_req_map);
asd_free_dma_mem(asd,
port->dc.smp_resp_dmat,
&port->dc.smp_resp_map);
return (-ENOMEM);
}
/* Fill in default settings. */
port->attr = (ASD_SSP_INITIATOR | ASD_SMP_INITIATOR |
ASD_STP_INITIATOR);
port->softc = (void *) asd;
port->state = ASD_PORT_UNUSED;
port->events = ASD_IDLE;
port->link_type = ASD_LINK_UNKNOWN;
port->management_type = ASD_DEVICE_NONE;
port->id = i;
asd->port_list[i] = port;
}
return (0);
}
/*
* Function:
* asd_hwi_alloc_scbs()
*
* Description:
* Allocate SCB buffers.
*/
static void
asd_hwi_alloc_scbs(struct asd_softc *asd)
{
struct scb *next_scb;
union hardware_scb *hscb;
struct map_node *hscb_map;
struct map_node *sg_map;
uint8_t *segs;
dma_addr_t hscb_busaddr;
dma_addr_t sg_busaddr;
int newcount;
int i;
if (asd->numscbs >= asd->hw_profile.max_scbs)
/* Can't allocate any more */
return;
if (asd->scbs_left != 0) {
int offset;
offset = (PAGE_SIZE / sizeof(*hscb)) - asd->scbs_left;
hscb_map = list_entry(asd->hscb_maps.next,
struct map_node, links);
hscb = &((union hardware_scb *)hscb_map->vaddr)[offset];
hscb_busaddr = hscb_map->busaddr + (offset * sizeof(*hscb));
} else {
hscb_map = asd_alloc_mem(sizeof(*hscb_map), GFP_ATOMIC);
if (hscb_map == NULL)
return;
/* Allocate the next batch of hardware SCBs */
if (asd_dmamem_alloc(asd, asd->hscb_dmat,
(void **) &hscb_map->vaddr, GFP_ATOMIC,
&hscb_map->dmamap,
&hscb_map->busaddr) != 0) {
asd_free_mem(hscb_map);
return;
}
list_add(&hscb_map->links, &asd->hscb_maps);
hscb = (union hardware_scb *)hscb_map->vaddr;
hscb_busaddr = hscb_map->busaddr;
asd->scbs_left = PAGE_SIZE / sizeof(*hscb);
asd_log(ASD_DBG_RUNTIME, "Mapped SCB data. %d SCBs left. "
"Total SCBs %d.\n",
asd->scbs_left, asd->numscbs);
}
if (asd->sgs_left != 0) {
int offset;
offset = ((asd_sglist_allocsize(asd) / asd_sglist_size(asd))
- asd->sgs_left) * asd_sglist_size(asd);
sg_map = list_entry(asd->sg_maps.next,
struct map_node, links);
segs = sg_map->vaddr + offset;
sg_busaddr = sg_map->busaddr + offset;
} else {
sg_map = asd_alloc_mem(sizeof(*sg_map), GFP_ATOMIC);
if (sg_map == NULL)
return;
/* Allocate the next batch of S/G lists */
if (asd_dmamem_alloc(asd, asd->sg_dmat,
(void **) &sg_map->vaddr, GFP_ATOMIC,
&sg_map->dmamap, &sg_map->busaddr) != 0) {
asd_free_mem(sg_map);
return;
}
list_add(&sg_map->links, &asd->sg_maps);
segs = sg_map->vaddr;
sg_busaddr = sg_map->busaddr;
asd->sgs_left =
asd_sglist_allocsize(asd) / asd_sglist_size(asd);
}
newcount = MIN(asd->scbs_left, asd->sgs_left);
newcount = MIN(newcount, (asd->hw_profile.max_scbs - asd->numscbs));
for (i = 0; i < newcount; i++) {
struct asd_scb_platform_data *pdata;
next_scb = (struct scb *) asd_alloc_mem(sizeof(*next_scb),
GFP_ATOMIC);
if (next_scb == NULL)
break;
memset(next_scb, 0, sizeof(*next_scb));
INIT_LIST_HEAD(&next_scb->hwi_links);
INIT_LIST_HEAD(&next_scb->owner_links);
pdata = asd_alloc_scb_platform_data(asd);
if (pdata == NULL) {
asd_free_mem(next_scb);
break;
}
next_scb->platform_data = pdata;
init_timer(&next_scb->platform_data->timeout);
next_scb->hscb_map = hscb_map;
next_scb->sg_map = sg_map;
next_scb->sg_list = (struct sg_element *)segs;
memset(hscb, 0, sizeof(*hscb));
next_scb->hscb = hscb;
next_scb->hscb_busaddr = asd_htole64(hscb_busaddr);
next_scb->sg_list_busaddr = sg_busaddr;
next_scb->softc = asd;
next_scb->flags = SCB_FLAG_NONE;
next_scb->eh_state = SCB_EH_NONE;
next_scb->hscb->header.index = asd_htole16(asd->numscbs);
asd->scbindex[asd_htole16(asd->numscbs)] = next_scb;
/* Add the scb to the free list. */
asd_hwi_free_scb(asd, next_scb);
hscb++;
hscb_busaddr += sizeof(*hscb);
segs += asd_sglist_size(asd);
sg_busaddr += asd_sglist_size(asd);
asd->numscbs++;
asd->scbs_left--;
asd->sgs_left--;
}
}
/*
* Function:
* asd_alloc_ddb
*
* Description:
* Allocate a DDB site on the controller.
* Returns ASD_INVALID_DDB_INDEX on failure.
* Returns DDB index on success.
*/
uint16_t
asd_alloc_ddb(struct asd_softc *asd)
{
u_int i;
u_int bit_index;
for (i = 0; i < asd->ddb_bitmap_size; i++) {
if (asd->free_ddb_bitmap[i] != ~0UL)
break;
}
if (i >= asd->ddb_bitmap_size)
return (ASD_INVALID_DDB_INDEX);
bit_index = ffz(asd->free_ddb_bitmap[i]);
asd->free_ddb_bitmap[i] |= (u_long)(1UL << bit_index);
return ((i * BITS_PER_LONG) + bit_index);
}
/*
* Function:
* asd_free_ddb
*
* Description:
* Mark the DDB site at "ddb_index" as free.
*/
void
asd_free_ddb(struct asd_softc *asd, uint16_t ddb_index)
{
u_int word_offset;
u_int bit_offset;
word_offset = ddb_index / BITS_PER_LONG;
bit_offset = ddb_index & (BITS_PER_LONG - 1);
asd->free_ddb_bitmap[word_offset] &= (u_long)(~(1UL << bit_offset));
}
/*
* Function:
* asd_hwi_setup_ddb_site()
*
* Description:
* Alloc and DDB site and setup the DDB site for the controller.
*/
int
asd_hwi_setup_ddb_site(struct asd_softc *asd, struct asd_target *target)
{
uint16_t ddb_index;
/* Allocate a free DDB site. */
ddb_index = asd_alloc_ddb(asd);
if (ddb_index == ASD_INVALID_DDB_INDEX)
return (-1);
target->ddb_profile.conn_handle = ddb_index;
asd_hwi_build_ddb_site(asd, target);
return (0);
}
/*
* Function:
* asd_hwi_init_sequencers()
*
* Description:
* Initialize the Central and Link Sequencers.
*/
static int
asd_hwi_init_sequencers(struct asd_softc *asd)
{
/* Pause the CSEQ. */
if (asd_hwi_pause_cseq(asd) != 0) {
asd_log(ASD_DBG_ERROR, "Failed to pause the CSEQ.\n");
return (-1);
}
/* Pause all the LSEQs. */
if (asd_hwi_pause_lseq(asd, asd->hw_profile.enabled_phys) != 0) {
asd_log(ASD_DBG_ERROR, "Failed to pause the LSEQs.\n");
return (-1);
}
/* Download the sequencers. */
if (asd_hwi_download_seqs(asd) != 0) {
asd_log(ASD_DBG_ERROR, "Failed to setup the SEQs.\n");
return (-1);
}
/*
* Zero out all of the ddb_sites
*/
asd_hwi_init_ddb_sites(asd);
/*
* Initialiaze the DDB site 0 and 1used internally by the
* sequencer.
*/
asd_hwi_init_internal_ddb(asd);
/* Setup and initialize the CSEQ and LSEQ(s). */
asd_hwi_setup_seqs(asd);
return (0);
}
/*
* Function:
* asd_hwi_get_scb()
*
* Description:
* Get a free SCB Desc from the free list if any.
*/
struct scb *
asd_hwi_get_scb(struct asd_softc *asd, int rsvd_pool)
{
struct scb *scb;
ASD_LOCK_ASSERT(asd);
if (rsvd_pool == 1) {
/* Get an SCB from the reserved pool. */
if (list_empty(&asd->rsvd_scbs)) {
/*
* We shouldn't be running out reserved SCBs.
*/
asd_log(ASD_DBG_ERROR, "Running out reserved SCBs.\n");
return (NULL);
}
scb = list_entry(asd->rsvd_scbs.next, struct scb, hwi_links);
scb->flags |= SCB_RESERVED;
#ifdef ASD_DEBUG
printk("reserved scb 0x%x is allocated\n", scb);
#endif
} else {
/* Get an SCB from the free pool. */
if (list_empty(&asd->free_scbs)) {
asd_hwi_alloc_scbs(asd);
if (list_empty(&asd->free_scbs)) {
#if 0
asd_log(ASD_DBG_ERROR,
"Failed to get a free SCB.\n");
#endif
return (NULL);
}
}
scb = list_entry(asd->free_scbs.next, struct scb, hwi_links);
}
list_del(&scb->hwi_links);
scb->post_stack_depth = 0;
return (scb);
}
/*
* Function:
* asd_hwi_enable_phy()
*
* Description:
* Enable the requested phy.
*/
int
asd_hwi_enable_phy(struct asd_softc *asd, struct asd_phy *phy)
{
struct scb *scb;
uint8_t phy_id;
u_long flags;
phy_id = phy->id;
#if SAS_COMSTOCK_SUPPORT
/*
* For COMSTOCK:
* 1. We need to setup OOB signal detection limits.
*/
asd_hwi_swb_write_byte(asd, LmSEQ_OOB_REG(phy_id, OOB_BFLTR), 0x40);
asd_hwi_swb_write_byte(asd, LmSEQ_OOB_REG(phy_id, OOB_INIT_MIN), 0x06);
asd_hwi_swb_write_byte(asd, LmSEQ_OOB_REG(phy_id, OOB_INIT_MAX), 0x13);
asd_hwi_swb_write_byte(asd, LmSEQ_OOB_REG(phy_id, OOB_INIT_NEG), 0x13);
asd_hwi_swb_write_byte(asd, LmSEQ_OOB_REG(phy_id, OOB_SAS_MIN), 0x13);
asd_hwi_swb_write_byte(asd, LmSEQ_OOB_REG(phy_id, OOB_SAS_MAX), 0x36);
asd_hwi_swb_write_byte(asd, LmSEQ_OOB_REG(phy_id, OOB_SAS_NEG), 0x36);
asd_hwi_swb_write_byte(asd, LmSEQ_OOB_REG(phy_id, OOB_WAKE_MIN), 0x02);
asd_hwi_swb_write_byte(asd, LmSEQ_OOB_REG(phy_id, OOB_WAKE_MAX), 0x06);
asd_hwi_swb_write_byte(asd, LmSEQ_OOB_REG(phy_id, OOB_WAKE_NEG), 0x06);
asd_hwi_swb_write_word(asd, LmSEQ_OOB_REG(phy_id, OOB_IDLE_MAX),
0x0080);
asd_hwi_swb_write_word(asd, LmSEQ_OOB_REG(phy_id, OOB_BURST_MAX),
0x0080);
/*
* 2. Put the OOB in slow clock mode. That corrects most of the
* other timer parameters including the signal transmit values
* for 37.5 MHZ.
*/
asd_hwi_swb_write_byte(asd, LmSEQ_OOB_REG(phy_id, OOB_MODE), SLOW_CLK);
#endif /* SAS_COMSTOCK_SUPPORT */
asd_hwi_swb_write_byte(asd, LmSEQ_OOB_REG(phy_id, INT_ENABLE_2), 0x0);
#if !SAS_COMSTOCK_SUPPORT
asd_hwi_swb_write_byte(asd, LmSEQ_OOB_REG(phy_id, HOT_PLUG_DELAY),
HOTPLUG_DEFAULT_DELAY);
/*
* Set the PHY SETTINGS values based on the manufacturing
* programmed values that we obtained from the NVRAM.
*/
asd_hwi_swb_write_byte(asd, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_0),
phy->phy_ctl0);
asd_hwi_swb_write_byte(asd, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_1),
phy->phy_ctl1);
asd_hwi_swb_write_byte(asd, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_2),
phy->phy_ctl2);
asd_hwi_swb_write_byte(asd, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_3),
phy->phy_ctl3);
#endif
#ifndef SEQUENCER_UPDATE
/* Initialize COMINIT_TIMER timeout. */
asd_hwi_swb_write_dword(asd, LmSEQ_COMINIT_TIMEOUT(phy_id),
SAS_DEFAULT_COMINIT_TIMEOUT);
#endif
/* Build Identify Frame address. */
asd_hwi_build_id_frame(phy);
/* Fill in bus address for Identify Frame buffer. */
asd_hwi_set_hw_addr(asd, LmSEQ_TX_ID_ADDR_FRAME(phy_id),
phy->id_addr_map.busaddr);
asd_hwi_control_activity_leds(asd, phy->id, ENABLE_PHY);
asd_lock(asd, &flags);
scb = asd_hwi_get_scb(asd, 0);
if (scb == NULL) {
#if defined(__VMKLNX__)
asd_unlock(asd, &flags);
#endif
asd_log(ASD_DBG_ERROR, "Failed to get a free SCB.\n");
return (-1);
}
/* Store the phy pointer. */
scb->io_ctx = (void *) phy;
scb->flags |= SCB_INTERNAL;
/* Build CONTROL PHY SCB. */
asd_hwi_build_control_phy(scb, phy, ENABLE_PHY);
list_add_tail(&scb->owner_links, &phy->pending_scbs);
asd_hwi_post_scb(asd, scb);
asd_unlock(asd, &flags);
return (0);
}
void
asd_hwi_release_sata_spinup_hold(
struct asd_softc *asd,
struct asd_phy *phy
)
{
struct scb *scb;
uint8_t phy_id;
u_long flags;
phy_id = phy->id;
asd_lock(asd, &flags);
scb = asd_hwi_get_scb(asd, 0);
if (scb == NULL) {
#if defined(__VMKLNX__)
asd_unlock(asd, &flags);
#endif
asd_log(ASD_DBG_ERROR, "Failed to get a free SCB.\n");
return;
}
/* Store the phy pointer. */
scb->io_ctx = (void *) phy;
scb->flags |= SCB_INTERNAL;
/* Build CONTROL PHY SCB. */
asd_hwi_build_control_phy(scb, phy, RELEASE_SPINUP_HOLD);
list_add_tail(&scb->owner_links, &phy->pending_scbs);
asd_hwi_post_scb(asd, scb);
asd_unlock(asd, &flags);
return;
}
void
asd_hwi_process_devint(struct asd_softc *asd)
{
uint32_t dchstatus;
unsigned link_num;
uint16_t break_addr;
uint32_t intval;
struct asd_step_data *step_datap;
dchstatus = asd_hwi_swb_read_dword(asd,
(DCH_SAS_REG_BASE_ADR + DCHSTATUS));
asd_dprint("DCHSTATUS = 0x%x\n", dchstatus);
step_datap = NULL;
if (dchstatus & LSEQINT_MASK) {
for (link_num = 0 ; link_num < ASD_MAX_PHYS ; link_num++) {
if ((dchstatus & (1 << link_num)) == 0) {
continue;
}
intval = asd_hwi_swb_read_dword(asd,
LmARP2INT(link_num));
asd_dprint("intval = 0x%x\n", intval);
#ifdef SEQUENCER_UPDATE
if (intval & ARP2BREAK0) {
break_addr = (asd_hwi_swb_read_dword(asd,
LmARP2BREAKADR01(link_num)) &
BREAKADR0_MASK) * 4;
#ifdef ASD_DEBUG
printk("LSEQ %d Break @ 0x%x\n",
link_num, break_addr);
#endif
step_datap = asd_hwi_alloc_step(asd);
asd_hwi_lseq_init_step(step_datap,
link_num);
asd_hwi_start_step_timer(step_datap);
asd_hwi_swb_write_dword(asd,
LmARP2INT(link_num),
ARP2BREAK0);
}
else if (intval & ARP2BREAK1) {
break_addr = (asd_hwi_swb_read_dword(asd,
LmARP2BREAKADR01(link_num)) &
BREAKADR1_MASK) * 4;
#ifdef ASD_DEBUG
printk("LSEQ %d Break @ 0x%x\n",
link_num, break_addr);
#endif
step_datap = asd_hwi_alloc_step(asd);
asd_hwi_lseq_init_step(step_datap,
link_num);
asd_hwi_start_step_timer(step_datap);
asd_hwi_swb_write_dword(asd,
LmARP2INT(link_num),
ARP2BREAK1);
}
else if (intval & ARP2BREAK2) {
break_addr = (asd_hwi_swb_read_dword(asd,
LmARP2BREAKADR23(link_num)) &
BREAKADR2_MASK) * 4;
#ifdef ASD_DEBUG
printk("LSEQ %d Break @ 0x%x\n",
link_num, break_addr);
#endif
step_datap = asd_hwi_alloc_step(asd);
asd_hwi_lseq_init_step(step_datap,
link_num);
asd_hwi_start_step_timer(step_datap);
asd_hwi_swb_write_dword(asd,
LmARP2INT(link_num),
ARP2BREAK2);
}
else if (intval & ARP2BREAK3) {
break_addr = (asd_hwi_swb_read_dword(asd,
LmARP2BREAKADR23(link_num)) &
BREAKADR3_MASK) * 4;
#ifdef ASD_DEBUG
printk("LSEQ %d Break @ 0x%x\n",
link_num, break_addr);
#endif
step_datap = asd_hwi_alloc_step(asd);
asd_hwi_lseq_init_step(step_datap,
link_num);
asd_hwi_start_step_timer(step_datap);
asd_hwi_swb_write_dword(asd,
LmARP2INT(link_num),
ARP2BREAK3);
}
#endif
if (intval & ARP2CIOPERR) {
#ifdef ASD_DEBUG
// asd_hwi_dump_seq_state(asd, 0xff);
//#else
asd_print("Fatal: ARP2CIOPERR\n");
#endif
}
asd_hwi_swb_write_dword(asd,
LmARP2INT(link_num), intval);
}
if (step_datap == NULL) {
asd_hwi_unpause_lseq(asd, link_num);
}
} else if (dchstatus & CSEQINT) {
intval = asd_hwi_swb_read_dword(asd, CARP2INT);
asd_dprint("intval = 0x%x\n", intval);
#ifdef SEQUENCER_UPDATE
if (intval & ARP2BREAK0) {
break_addr = (asd_hwi_swb_read_dword(asd,
CARP2BREAKADR01) & BREAKADR0_MASK) * 4;
#ifdef ASD_DEBUG
printk("CSEQ Break @ 0x%x\n", break_addr);
#endif
step_datap = asd_hwi_alloc_step(asd);
if (asd_hwi_cseq_init_step(step_datap) != 0) {
asd_hwi_start_step_timer(step_datap);
} else {
asd_hwi_free_step(step_datap);
}
asd_hwi_swb_write_dword(asd, CARP2INT, ARP2BREAK0);
}
#endif
if (intval & ARP2CIOPERR) {
#ifdef ASD_DEBUG
// asd_hwi_dump_seq_state(asd, 0xff);
//#else
asd_print("Fatal: ARP2CIOPERR\n");
#endif
}
asd_hwi_swb_write_dword(asd, CARP2INT, intval);
}
}
//JD
#ifdef ASD_DEBUG
typedef struct state_name {
uint8_t name[16];
uint32_t status;
} state_name_t;
static state_name_t CHIMINT_STATUS[] =
{
{"EXT_INT0", 0x00000800},
{"EXT_INT1", 0x00000400},
{"PORRSTDET", 0x00000200},
{"HARDRSTDET", 0x00000100},
{"DLAVAILQ", 0x00000080}, /* ro */
{"HOSTERR", 0x00000040},
{"INITERR", 0x00000020},
{"DEVINT", 0x00000010},
{"COMINT", 0x00000008},
{"DEVTIMER2", 0x00000004},
{"DEVTIMER1", 0x00000002},
{"DLAVAIL", 0x00000001},
{"", 0 } /* Last entry should be NULL. */
};
/*
* Function:
* dump_CHIMINT()
*
* Description:
* Display CHIMINT Status (from IRQ).
*/
void dump_CHIMINT(uint32_t intstate)
{
int i;
asd_log(ASD_DBG_INFO, "asd_process_irq: CHIMINT is (0x%x):\n",intstate);
for(i=0;CHIMINT_STATUS[i].status!=0;i++)
{
if(intstate & CHIMINT_STATUS[i].status) asd_log(ASD_DBG_INFO, "- %s\n",CHIMINT_STATUS[i].name);
}
}
#endif //ASD_DEBUG
/*
* Function:
* asd_hwi_process_irq()
*
* Description:
* Process any interrupts pending for our controller.
*/
int
asd_hwi_process_irq(struct asd_softc *asd)
{
struct asd_done_list *dl_entry;
int irq_processed;
uint32_t intstat;
ASD_LOCK_ASSERT(asd);
/*
* Check if any DL entries need to be processed. If so,
* bypass a costly read of our interrupt status register
* and assume that the done list entries are the cause of
* our interrupt.
*/
dl_entry = &asd->done_list[asd->dl_next];
if ((dl_entry->toggle & ASD_DL_TOGGLE_MASK) == asd->dl_valid)
intstat = DLAVAIL;
else
intstat = asd_read_dword(asd, CHIMINT);
if (intstat & DLAVAIL) {
asd_write_dword(asd, CHIMINT, DLAVAIL);
/*
* Ensure that the chip sees that we've cleared
* this interrupt before we walk the done_list.
* Otherwise, we may, due to posted bus writes,
* clear the interrupt after we finish the scan,
* and after the sequencer has added new entries
* and asserted the interrupt again.
*
* NOTE: This extra read, and in fact the clearing
* of the command complete interrupt, will
* not be needed on systems using MSI.
*/
asd_flush_device_writes(asd);
asd_hwi_process_dl(asd);
irq_processed = 1;
} else if ((intstat & CHIMINT_MASK) != 0) {
if ((intstat & DEVINT) != 0) {
//#ifdef ASD_DEBUG
printk("DEVINT intstat 0x%x\n", intstat);
//#endif
asd_hwi_process_devint(asd);
//asd_hwi_dump_seq_state(asd, 0xff);
asd_write_dword(asd, CHIMINT, DEVINT);
irq_processed = 1;
} else {
//#ifdef ASD_DEBUG
printk("unknown interrupt 0x%x\n", intstat);
//#endif
asd_write_dword(asd, CHIMINT, intstat);
#ifdef ASD_DEBUG
dump_CHIMINT(intstat);
asd_hwi_dump_seq_state(asd, 0xff);
#endif
}
irq_processed = 1;
} else {
irq_processed = 0;
}
return (irq_processed);
}
/*
* Function:
* asd_hwi_process_dl()
*
* Description:
* Process posted Done List entries.
*/
static void
asd_hwi_process_dl(struct asd_softc *asd)
{
struct asd_done_list *dl_entry;
struct scb *scb;
/*
* Look for entries in the done list that have completed.
* The valid_tag completion field indicates the validity
* of the entry - the valid value toggles each time through
* the queue.
*/
if ((asd->flags & ASD_RUNNING_DONE_LIST) != 0)
panic("asd_hwi_process_dl recursion");
asd->flags |= ASD_RUNNING_DONE_LIST;
for (;;) {
dl_entry = &asd->done_list[asd->dl_next];
if ((dl_entry->toggle & ASD_DL_TOGGLE_MASK) != asd->dl_valid)
break;
scb = asd->scbindex[dl_entry->index];
//JD
#ifdef ASD_DEBUG
#if 0
if(asd->debug_flag==1)
{
// asd_log(ASD_DBG_INFO, "asd_hwi_process_dl: dumping SCSI cmd LBA 0x%02x%02x%02x%02x - 0x%02x%02x , opcode 0x%x.\n",
// scb->io_ctx->scsi_cmd.cmnd[2],
// scb->io_ctx->scsi_cmd.cmnd[3],
// scb->io_ctx->scsi_cmd.cmnd[4],
// scb->io_ctx->scsi_cmd.cmnd[5],
// scb->io_ctx->scsi_cmd.cmnd[7],
// scb->io_ctx->scsi_cmd.cmnd[8],
// scb->io_ctx->scsi_cmd.cmnd[0]);
//
// asd_log(ASD_DBG_INFO, "scb ptr=%p dl_next=%d dl ptr=%p op=%x index = %x\n", scb,asd->dl_next,dl_entry,
// dl_entry->opcode,dl_entry->index);
asd_log(ASD_DBG_INFO, "scb ptr=%p opcode=%x index=%x\n", scb,dl_entry->opcode,dl_entry->index);
}
#endif
#endif
if ((scb->flags & SCB_PENDING) != 0) {
list_del(&scb->hwi_links);
scb->flags &= ~SCB_PENDING;
}
/* Process DL Entry. */
switch (dl_entry->opcode) {
case TASK_COMP_WO_ERR:
case TASK_COMP_W_UNDERRUN:
case TASK_COMP_W_OVERRUN:
case TASK_F_W_OPEN_REJECT:
case TASK_INT_W_BRK_RCVD:
case TASK_INT_W_PROT_ERR:
case SSP_TASK_COMP_W_RESP:
case TASK_INT_W_PHY_DOWN:
case LINK_ADMIN_TASK_COMP_W_RESP:
case CSMI_TASK_COMP_WO_ERR:
case ATA_TASK_COMP_W_RESP:
case TASK_INT_W_NAK_RCVD:
case RESUME_COMPLETE:
case TASK_INT_W_ACKNAK_TO:
case TASK_F_W_SMPRSP_TO:
case TASK_F_W_SMP_XMTRCV_ERR:
case TASK_F_W_NAK_RCVD:
case TASK_ABORTED_BY_ITNL_EXP:
case ATA_TASK_COMP_W_R_ERR_RCVD:
case TMF_F_W_TC_NOT_FOUND:
case TASK_ABORTED_ON_REQUEST:
case TMF_F_W_TAG_NOT_FOUND:
case TMF_F_W_TAG_ALREADY_FREE:
case TMF_F_W_TASK_ALREADY_DONE:
case TMF_F_W_CONN_HNDL_NOT_FOUND:
case TASK_CLEARED:
case TASK_UA_W_SYNCS_RCVD:
case TASK_UNACKED_W_BREAK_RCVD:
case TASK_UNACKED_W_ACKNAK_TIMEOUT:
asd_pop_post_stack(asd, scb, dl_entry);
break;
case CONTROL_PHY_TASK_COMP:
{
struct control_phy_sb *cntrl_phy;
cntrl_phy = &dl_entry->stat_blk.control_phy;
if (cntrl_phy->sb_opcode == PHY_RESET_COMPLETED) {
asd_hwi_process_phy_comp(asd, scb, cntrl_phy);
} else {
asd_log(ASD_DBG_RUNTIME, "Invalid status "
"block upcode.\n");
}
/*
* Post routine needs to be called if the
* CONTROL PHY is issued as result of error recovery
* process or from CSMI.
*/
if ((scb->flags & SCB_RECOVERY) != 0)
asd_pop_post_stack(asd, scb, dl_entry);
break;
}
default:
/*
* Making default case for EDB received and
* and non supported DL opcode.
*/
if ((dl_entry->opcode >= 0xC1) &&
(dl_entry->opcode <= 0xC7))
asd_hwi_process_edb(asd, dl_entry);
else
asd_log(ASD_DBG_RUNTIME,
"Received unsupported "
"DL entry (opcode = 0x%x).\n",
dl_entry->opcode);
break;
}
asd->dl_next = (asd->dl_next + 1) & asd->dl_wrap_mask;
if (asd->dl_next == 0)
asd->dl_valid ^= ASD_DL_TOGGLE_MASK;
}
//JD
#ifdef ASD_DEBUG
// asd->debug_flag=0;
#endif
asd->flags &= ~ASD_RUNNING_DONE_LIST;
}
/*
* Function:
* asd_hwi_process_phy_comp()
*
* Description:
* Process phy reset completion.
*/
static void
asd_hwi_process_phy_comp(struct asd_softc *asd, struct scb *scb,
struct control_phy_sb *cntrl_phy)
{
struct asd_phy *phy;
struct asd_control_phy_hscb *cntrlphy_scb;
cntrlphy_scb = &scb->hscb->control_phy;
phy = (struct asd_phy *) scb->io_ctx;
switch (cntrlphy_scb->sub_func) {
case DISABLE_PHY:
{
asd->hw_profile.enabled_phys &= ~(1 << phy->id);
phy->state = ASD_PHY_OFFLINE;
/*
* Check if this phy is attached to a target.
*/
if (phy->src_port != NULL) {
/*
* DC: Currently, we treat this similar to loss of
* signal scenario.
* Need to examine the behavior once the phy is
* is disabled !!
* Prior to disabling the phy that has target
* connected, we need to abort all outstanding
* IO to the affected target ports.
*/
phy->attr = (ASD_SSP_INITIATOR | ASD_SMP_INITIATOR |
ASD_STP_INITIATOR);
phy->src_port->events |= ASD_LOSS_OF_SIGNAL;
asd_wakeup_sem(&asd->platform_data->discovery_sem);
}
list_del(&scb->owner_links);
asd_hwi_free_scb(asd, scb);
break;
}
case ENABLE_PHY:
/* Check the OOB status from the link reset sequence. */
if (cntrl_phy->oob_status & CURRENT_OOB_DONE) {
if ((asd->hw_profile.enabled_phys &
(1 << phy->id)) == 0)
asd->hw_profile.enabled_phys |= (1 << phy->id);
/* There is a device attached. */
if (cntrl_phy->oob_status & CURRENT_DEVICE_PRESENT) {
phy->attr |= ASD_DEVICE_PRESENT;
if (cntrl_phy->oob_status & CURRENT_SPINUP_HOLD)
phy->attr |= ASD_SATA_SPINUP_HOLD;
phy->state = ASD_PHY_WAITING_FOR_ID_ADDR;
} else {
phy->state = ASD_PHY_ONLINE;
}
/* Get the negotiated connection rate. */
if (cntrl_phy->oob_mode & PHY_SPEED_30)
phy->conn_rate = SAS_30GBPS_RATE;
else if (cntrl_phy->oob_mode & PHY_SPEED_15)
phy->conn_rate = SAS_15GBPS_RATE;
/* Get the transport mode. */
if (cntrl_phy->oob_mode & SAS_MODE)
phy->attr |= ASD_SAS_MODE;
else if (cntrl_phy->oob_mode & SATA_MODE)
phy->attr |= ASD_SATA_MODE;
} else if (cntrl_phy->oob_status & CURRENT_SPINUP_HOLD) {
/*
* SATA target attached that has not been transmitted
* COMWAKE (spun-up).
*/
asd_log(ASD_DBG_RUNTIME, "CURRENT SPINUP HOLD.\n");
phy->attr |= ASD_SATA_SPINUP_HOLD;
phy->state = ASD_PHY_WAITING_FOR_ID_ADDR;
} else if (cntrl_phy->oob_status & CURRENT_ERR_MASK) {
asd_log(ASD_DBG_ERROR, "OOB ERROR.\n");
phy->state = ASD_PHY_OFFLINE;
} else {
/*
* This should be the case when no device is
* connected.
*/
phy->state = ASD_PHY_ONLINE;
}
#ifdef ASD_TEST
asd_hwi_dump_phy(phy);
#endif
if ((scb->flags & SCB_RECOVERY) == 0) {
list_del(&scb->owner_links);
asd_hwi_free_scb(asd, scb);
asd_wakeup_sem(&asd->platform_data->discovery_sem);
} else {
if (phy->state == ASD_PHY_OFFLINE)
scb->eh_status = SCB_EH_FAILED;
else
scb->eh_status = SCB_EH_SUCCEED;
}
break;
case RELEASE_SPINUP_HOLD:
/* To be implemented */
asd_log(ASD_DBG_RUNTIME,
"CONTROL PHY : RELEASE SPINUP HOLD.\n");
break;
case PHY_NO_OP:
asd_log(ASD_DBG_RUNTIME, "CONTROL PHY : PHY NO OP.\n");
if ((scb->flags & SCB_RECOVERY) != 0) {
/*
* PHY NO OP control completion. The phy no op was
* issued after HARD RESET completion.
*/
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_SUCCEED;
}
break;
case EXECUTE_HARD_RESET:
asd_log(ASD_DBG_RUNTIME,"CONTROL PHY : EXECUTE HARD RESET.\n");
if ((scb->flags & SCB_RECOVERY) != 0) {
/*
* Upon HARD RESET completion, we need to issue
* PHY NO OP control to enable the hot-plug timer
* which was disabled prior to issuing HARD RESET.
*/
scb->eh_state = SCB_EH_PHY_NO_OP_REQ;
scb->eh_status = SCB_EH_SUCCEED;
}
break;
default:
asd_log(ASD_DBG_RUNTIME,
"CONTROL PHY : INVALID SUBFUNC OPCODE.\n");
break;
}
return;
}
#ifdef ASD_TEST
static void
asd_hwi_dump_phy(struct asd_phy *phy)
{
u_char i;
struct asd_port *port;
port = phy->src_port;
asd_print("Phy Id = 0x%x.\n", phy->id);
asd_print("Phy attr = 0x%x.\n", phy->attr);
asd_print("Phy state = 0x%x.\n", phy->state);
asd_print("Phy conn_rate = 0x%x.\n", phy->conn_rate);
asd_print("Phy src port = %p.\n", phy->src_port);
for (i = 0; i < 8; i++)
asd_print("Phy %d SAS ADDR[%d]=0x%x.\n", phy->id, i,
phy->sas_addr[i]);
}
#endif
union edb *
asd_hwi_indexes_to_edb(struct asd_softc *asd, struct scb **pscb,
u_int escb_index, u_int edb_index)
{
struct scb *scb;
struct asd_empty_hscb *escb;
struct empty_buf_elem *ebe;
if (escb_index > asd->hw_profile.max_scbs)
return (NULL);
scb = asd->scbindex[escb_index];
if (scb == NULL)
return (NULL);
escb = &scb->hscb->empty_scb;
ebe = &escb->buf_elem[edb_index];
if (ELEM_BUFFER_VALID_FIELD(ebe) != ELEM_BUFFER_VALID)
return (NULL);
*pscb = scb;
return (asd_hwi_get_edb_vaddr(asd, asd_le64toh(ebe->busaddr)));
}
/*
* Function:
* asd_hwi_process_edb()
*
* Description:
* Process Empty Data Buffer that was posted by the sequencer.
*/
static void
asd_hwi_process_edb(struct asd_softc *asd, struct asd_done_list *dl_entry)
{
struct edb_rcvd_sb *edbr;
union edb *edb;
struct scb *scb;
struct asd_phy *phy;
u_char phy_id;
u_char elem_id;
edbr = &dl_entry->stat_blk.edb_rcvd;
elem_id = (dl_entry->opcode & EDB_OPCODE_MASK) - 1;
phy_id = edbr->sb_opcode & EDB_OPCODE_MASK;
phy = asd->phy_list[phy_id];
edbr->sb_opcode &= ~EDB_OPCODE_MASK;
edb = asd_hwi_indexes_to_edb(asd, &scb,
asd_le16toh(dl_entry->index),
elem_id);
switch (edbr->sb_opcode) {
case BYTES_DMAED:
{
struct bytes_dmaed_subblk *bytes_dmaed;
u_int bytes_rcvd;
bytes_dmaed = &edbr->edb_subblk.bytes_dmaed;
bytes_rcvd = asd_le16toh(bytes_dmaed->edb_len) &
BYTES_DMAED_LEN_MASK;
if (bytes_rcvd > sizeof(union sas_bytes_dmaed))
bytes_rcvd = sizeof(union sas_bytes_dmaed);
memcpy(&phy->bytes_dmaed_rcvd.id_addr_rcvd, edb, bytes_rcvd);
phy->events |= ASD_ID_ADDR_RCVD;
phy->state = ASD_PHY_WAITING_FOR_ID_ADDR;
asd_wakeup_sem(&asd->platform_data->discovery_sem);
#ifdef ASD_TEST
asd_hwi_dump_phy_id_addr(phy);
#endif
break;
}
case PRIMITIVE_RCVD:
{
struct primitive_rcvd_subblk *prim_rcvd;
prim_rcvd = &edbr->edb_subblk.prim_rcvd;
asd_log(ASD_DBG_RUNTIME,
"EDB: PRIMITIVE RCVD. Addr = 0x%x, Cont = 0x%x\n",
prim_rcvd->reg_addr, prim_rcvd->reg_content);
/*
* Only process primitive for phy(s) that already associated
* with port.
*/
if (phy->src_port != NULL)
asd_hwi_process_prim_event(asd, phy,
prim_rcvd->reg_addr,
prim_rcvd->reg_content);
break;
}
case PHY_EVENT:
{
struct phy_event_subblk *phy_event;
phy_event = &edbr->edb_subblk.phy_event;
asd_log(ASD_DBG_RUNTIME,
"EDB: PHY_EVENT. Stat 0x%x, Mode 0x%x, Sigs = 0x%x\n",
phy_event->oob_status, phy_event->oob_mode,
phy_event->oob_signals);
phy_event->oob_status &= CURRENT_PHY_MASK;
asd_hwi_process_phy_event(asd, phy,
phy_event->oob_status,
phy_event->oob_mode);
break;
}
case LINK_RESET_ERR:
{
struct link_reset_err_subblk *link_rst;
link_rst = &edbr->edb_subblk.link_reset_err;
asd_log(ASD_DBG_RUNTIME, "EDB: LINK RESET ERRORS. \n");
asd_log(ASD_DBG_RUNTIME, "Timedout waiting %s from Phy %d.\n",
((link_rst->error == RCV_FIS_TIMER_EXP) ?
"Initial Device-to-Host Register FIS" :
"IDENTITY Address Frame"),
phy_id);
asd_hwi_handle_link_rst_err(asd, phy);
break;
}
case TIMER_EVENT:
{
struct timer_event_subblk *timer_event;
timer_event = &edbr->edb_subblk.timer_event;
asd_log(ASD_DBG_RUNTIME, "EDB: TIMER EVENT. Error = 0x%x \n",
timer_event->error);
asd_hwi_process_timer_event(asd, phy, timer_event->error);
break;
}
case REQ_TASK_ABORT:
{
struct req_task_abort_subblk *req_task_abort;
asd_log(ASD_DBG_RUNTIME, "EDB: REQUEST TASK ABORT. \n");
req_task_abort = &edbr->edb_subblk.req_task_abort;
asd_log(ASD_DBG_RUNTIME, "Req TC to Abort = 0x%x, "
"Reason = 0x%x.\n", req_task_abort->task_tc_to_abort,
req_task_abort->reason);
asd_hwi_process_req_task(asd, edbr->sb_opcode,
req_task_abort->task_tc_to_abort);
break;
}
case REQ_DEVICE_RESET:
{
struct req_dev_reset_subblk *req_dev_reset;
asd_log(ASD_DBG_RUNTIME, "EDB: REQUEST DEVICE RESET. \n");
req_dev_reset = &edbr->edb_subblk.req_dev_reset;
asd_log(ASD_DBG_RUNTIME, "Req TC to Reset = 0x%x, "
"Reason = 0x%x.\n", req_dev_reset->task_tc_to_abort,
req_dev_reset->reason);
asd_hwi_process_req_task(asd, edbr->sb_opcode,
req_dev_reset->task_tc_to_abort);
break;
}
default:
asd_log(ASD_DBG_RUNTIME, "Invalid EDB opcode.\n");
break;
}
asd_hwi_free_edb(asd, scb, (elem_id));
}
/*
* Function:
* asd_hwi_process_prim_event()
*
* Description:
* Process any recevied primitives that are not handled by the
* firmware (eg. BROADCAST, HARD_RESET, etc.)
*/
static void
asd_hwi_process_prim_event(struct asd_softc *asd, struct asd_phy *phy,
u_int reg_addr, u_int reg_content)
{
uint32_t reg_val;
reg_val = 0;
if (reg_addr == LmPRMSTAT0BYTE1) {
/*
* First byte of Primitive Status register is intended for
* BROADCAST primitives.
*/
reg_val = (reg_content << 8) & 0xFF00;
switch (reg_val) {
case LmBROADCH:
case LmBROADRVCH0:
case LmBROADRVCH1:
asd_log(ASD_DBG_RUNTIME, "BROADCAST PRIMITIVE "
"received.\n");
/*
* Set the event that discovery is needed and
* wakeup discovery thread.
*/
if(phy->src_port->events & ASD_DISCOVERY_PROCESS)
phy->src_port->events |= ASD_DISCOVERY_RETRY;
else
phy->src_port->events = ASD_DISCOVERY_REQ;
asd_wakeup_sem(&asd->platform_data->discovery_sem);
phy->brdcst_rcvd_cnt++;
break;
default:
asd_log(ASD_DBG_ERROR, "Unsupported BROADCAST "
"primitive.\n");
break;
}
} else if (reg_addr == LmPRMSTAT1BYTE0) {
reg_val = reg_content & 0xFF;
if (reg_val == LmHARDRST) {
asd_log(ASD_DBG_RUNTIME, "HARD_RESET primitive "
"received.\n");
}
} else if (reg_addr == LmPRMSTAT0BYTE3) {
reg_val = (reg_content << 24) & 0xFF000000;
if (reg_val == LmUNKNOWNP) {
asd_log(ASD_DBG_RUNTIME, "Undefined primitive "
"received.\n");
}
} else {
asd_log(ASD_DBG_ERROR, "Unsupported PRIMITIVE STATUS REG.\n");
}
}
/*
* Function:
* asd_hwi_process_phy_event()
*
* Description:
* Process received async. phy events.
*/
static void
asd_hwi_process_phy_event(struct asd_softc *asd, struct asd_phy *phy,
u_int oob_status, u_int oob_mode)
{
switch (oob_status) {
case DEVICE_REMOVED:
/*
* We received a phy event that notified us that the
* signal is lost with the direct attached device to
* this phy. The device has been hot removed.
*/
asd_log(ASD_DBG_RUNTIME,
"PHY_EVENT (%d) - DEVICE HOT REMOVED.\n", phy->id);
phy->state = ASD_PHY_ONLINE;
phy->attr = (ASD_SSP_INITIATOR | ASD_SMP_INITIATOR |
ASD_STP_INITIATOR);
if (phy->src_port != NULL)
phy->src_port->events |= ASD_LOSS_OF_SIGNAL;
asd_wakeup_sem(&asd->platform_data->discovery_sem);
break;
case DEVICE_ADDED_W_CNT:
case DEVICE_ADDED_WO_CNT:
asd_log(ASD_DBG_RUNTIME,
"PHY_EVENT (%d) - DEVICE HOT ADDED.\n", phy->id);
/* There is a device attached. */
if (oob_status & CURRENT_DEVICE_PRESENT) {
phy->attr |= ASD_DEVICE_PRESENT;
if (oob_status & CURRENT_SPINUP_HOLD)
phy->attr |= ASD_SATA_SPINUP_HOLD;
phy->state = ASD_PHY_WAITING_FOR_ID_ADDR;
}
/* Get the negotiated connection rate. */
if (oob_mode & PHY_SPEED_30) {
phy->conn_rate = SAS_30GBPS_RATE;
} else if (oob_mode & PHY_SPEED_15) {
phy->conn_rate = SAS_15GBPS_RATE;
}
/* Get the transport mode. */
if (oob_mode & SAS_MODE) {
phy->attr |= ASD_SAS_MODE;
} else if (oob_mode & SATA_MODE) {
phy->attr |= ASD_SATA_MODE;
}
break;
case CURRENT_OOB1_ERROR:
case CURRENT_OOB2_ERROR:
asd_print("PHY_EVENT (%d) - OOB ERROR.\n", phy->id);
break;
default:
asd_log(ASD_DBG_ERROR,
"PHY_EVENT (%d) - UNKNOWN EVENT 0x%x.\n", phy->id,
oob_status);
break;
}
}
/*
* Function:
* asd_hwi_process_timer_event()
*
* Description:
* Process received async. timer events.
*/
static void
asd_hwi_process_timer_event(struct asd_softc *asd, struct asd_phy *phy, uint8_t error)
{
switch (error) {
case DWS_RESET_TO_EXP:
/*
* We received a DWS timer event that the direct attached device may be lost,
* let's remove the device and restart a discovery.
*/
asd_log(ASD_DBG_RUNTIME,
"TIMER_EVENT (%d) - DWS_RESET_TO_EXP.\n", phy->id);
phy->state = ASD_PHY_ONLINE;
phy->attr = (ASD_SSP_INITIATOR | ASD_SMP_INITIATOR |
ASD_STP_INITIATOR);
if (phy->src_port != NULL)
phy->src_port->events |= ASD_LOSS_OF_SIGNAL;
asd_wakeup_sem(&asd->platform_data->discovery_sem);
break;
default:
asd_log(ASD_DBG_ERROR,
"TIMER_EVENT (%d) - UNKNOWN EVENT 0x%x.\n", phy->id,
error);
break;
}
}
#ifdef ASD_TEST
static void
asd_hwi_dump_phy_id_addr(struct asd_phy *phy)
{
u_char i;
asd_print("ID ADDRESS FRAME RECEIVED.\n");
asd_print("Addr Frame Type = 0x%x.\n",
phy->bytes_dmaed_rcvd.id_addr_rcvd.addr_frame_type);
asd_print("Init Port Type = 0x%x.\n",
phy->bytes_dmaed_rcvd.id_addr_rcvd.init_port_type);
asd_print("Tgt Port Type = 0x%x.\n",
phy->bytes_dmaed_rcvd.id_addr_rcvd.tgt_port_type);
asd_print("Phy ID = 0x%x.\n",
phy->bytes_dmaed_rcvd.id_addr_rcvd.phy_id);
for (i = 0; i < 8; i++)
asd_print("TGT Sas Addr[%d] = 0x%x.\n",
i, phy->bytes_dmaed_rcvd.id_addr_rcvd.sas_addr[i]);
}
#endif
/*
* Function:
* asd_hwi_handle_link_rst_err()
*
* Description:
* Handle Link Reset Error event as a result of timedout while
* waiting for Identity Frame Address or Initial Device-to-Host
* Register FIS from direct-attached device.
*/
static void
asd_hwi_handle_link_rst_err(struct asd_softc *asd, struct asd_phy *phy)
{
struct scb *scb;
/*
* We are skipping OOB register initialization as it was done
* the first time we enable the phy.
* Should we redo this initialization again??
*/
/*
* We want to retry the link reset sequence up to a certain
* amount of time to retry establishing connection with the device.
*/
if (phy->link_rst_cnt > MAX_LINK_RESET_RETRY) {
/*
* We have tried link reset a few times, the device still
* failed to return the ID Frame Addr or Device-to-Host
* Register FIS.
* End the discovery process for this phy.
*/
phy->state = ASD_PHY_ONLINE;
phy->attr = (ASD_SSP_INITIATOR | ASD_SMP_INITIATOR |
ASD_STP_INITIATOR);
asd_wakeup_sem(&asd->platform_data->discovery_sem);
}
if ((scb = asd_hwi_get_scb(asd, 0)) == NULL) {
asd_log(ASD_DBG_ERROR, "Out of SCB resources.\n");
return;
}
scb->io_ctx = (void *) phy;
scb->flags |= SCB_INTERNAL;
asd_hwi_build_control_phy(scb, phy, ENABLE_PHY);
list_add_tail(&scb->owner_links, &phy->pending_scbs);
phy->link_rst_cnt++;
asd_hwi_post_scb(asd, scb);
}
/*
* Function:
* asd_hwi_process_req_task()
*
* Description:
* Process the requested task recevied from the sequencer.
*/
static void
asd_hwi_process_req_task(struct asd_softc *asd, uint8_t req_type,
uint16_t index)
{
struct scb *scb;
int found;
if ((req_type != REQ_TASK_ABORT) && (req_type != REQ_DEVICE_RESET)) {
asd_log(ASD_DBG_ERROR, "Unsupported REQ TASK 0x%x.\n",
req_type);
return;
}
found = 0;
list_for_each_entry(scb, &asd->platform_data->pending_os_scbs,
owner_links) {
if (SCB_GET_INDEX(scb) == index) {
found = 1;
break;
}
}
if (found == 0) {
asd_log(ASD_DBG_ERROR, "REQ TASK with invalid TC.\n");
#ifdef DEBUG_DDB
#ifdef ASD_DEBUG
{
u_long lseqs_to_dump;
u_int lseq_id;
int indx;
for(indx=0;indx< asd->ddb_bitmap_size; indx++)
{
lseqs_to_dump = asd->free_ddb_bitmap[indx];
lseq_id = 0;
while (lseqs_to_dump != 0) {
for ( ; lseq_id < (8 * sizeof(u_long)); lseq_id++) {
if (lseqs_to_dump & (1UL << lseq_id)) {
lseqs_to_dump &= ~(1UL << lseq_id);
break;
}
}
/* Dump out specific LSEQ Registers state. */
asd_hwi_dump_ssp_smp_ddb_site(asd, lseq_id + (indx * 8 * sizeof(ulong)));
}
}
}
asd_hwi_dump_seq_state(asd, asd->hw_profile.enabled_phys);
#endif
#endif
return;
}
if (req_type == REQ_TASK_ABORT)
scb->eh_state = SCB_EH_ABORT_REQ;
else
scb->eh_state = SCB_EH_DEV_RESET_REQ;
scb->flags |= SCB_TIMEDOUT;
scb->eh_post = asd_hwi_req_task_done;
list_add_tail(&scb->timedout_links, &asd->timedout_scbs);
asd_wakeup_sem(&asd->platform_data->ehandler_sem);
}
static void
asd_hwi_req_task_done(struct asd_softc *asd, struct scb *scb)
{
asd_log(ASD_DBG_ERROR, "Req Task completed.\n");
}
/*************** Helper Functions to build a specific SCB type. ***************/
/*
* Function:
* asd_hwi_build_id_frame()
*
* Description:
* Build an Identify Frame address.
*/
static void
asd_hwi_build_id_frame(struct asd_phy *phy)
{
struct sas_id_addr *id_addr;
u_char i;
id_addr = (struct sas_id_addr *) phy->id_addr_map.vaddr;
memset(id_addr, 0x0, sizeof(*id_addr));
/* Set the device type to end-device. */
id_addr->addr_frame_type |= SAS_END_DEVICE;
for (i = 0; i < SAS_ADDR_LEN; i++)
id_addr->sas_addr[i] = phy->sas_addr[i];
/* Set the Initiator Port attributes. */
id_addr->init_port_type = (SSP_INIT_PORT | STP_INIT_PORT |
SMP_INIT_PORT);
id_addr->phy_id = phy->id;
}
/*
* Function:
* asd_hwi_build_control_phy()
*
* Description:
* Build a CONTROL PHY SCB.
* CONTROL PHY SCB is used to control the operation of a phy, such as
* enable or disable phy, execute hard reset, release spinup hold and
* control ATA device.
*/
void
asd_hwi_build_control_phy(struct scb *scb, struct asd_phy *phy,
uint8_t sub_func)
{
struct asd_control_phy_hscb *cntrlphy_hscb;
uint8_t phy_id;
uint8_t speed_mask;
speed_mask = 0;
phy_id = phy->id;
cntrlphy_hscb = &scb->hscb->control_phy;
cntrlphy_hscb->header.opcode = SCB_CONTROL_PHY;
cntrlphy_hscb->phy_id = phy_id;
cntrlphy_hscb->sub_func = sub_func;
if ((cntrlphy_hscb->sub_func == ENABLE_PHY) ||
(cntrlphy_hscb->sub_func == EXECUTE_HARD_RESET) ||
(cntrlphy_hscb->sub_func == PHY_NO_OP)) {
cntrlphy_hscb->func_mask = FUNCTION_MASK_DEFAULT;
/*
* Hot Plug timer needs to be disabled while performing
* Hard Reset.
*/
if (cntrlphy_hscb->sub_func == EXECUTE_HARD_RESET)
cntrlphy_hscb->func_mask |= HOT_PLUG_DIS;
/* mask all speeds */
speed_mask = (SAS_SPEED_60_DIS | SAS_SPEED_30_DIS |
SAS_SPEED_15_DIS | SATA_SPEED_30_DIS |
SATA_SPEED_15_DIS);
/* enable required speed */
asd_hwi_set_speed_mask(phy->max_link_rate, &speed_mask);
asd_hwi_set_speed_mask(phy->min_link_rate, &speed_mask);
/* Razor should enable 1.5 Gbs and disable 3 Gbs for SATA */
speed_mask &= ~SATA_SPEED_15_DIS;
speed_mask |= SATA_SPEED_30_DIS;
#if SAS_COMSTOCK_SUPPORT
/* COMSTOCK only support 1.5 Gbits/s data transfer. */
speed_mask &= ~SATA_SPEED_15_DIS;
cntrlphy_hscb->speed_mask = speed_mask | (SATA_SPEED_30_DIS |
SAS_SPEED_60_DIS |
SAS_SPEED_30_DIS);
#else
cntrlphy_hscb->speed_mask = speed_mask;
#endif
/* Set to Hot plug time delay to 100 ms. */
cntrlphy_hscb->hot_plug_delay = HOTPLUG_DEFAULT_DELAY;
cntrlphy_hscb->port_type = (SSP_INITIATOR_PORT |
STP_INITIATOR_PORT |
SMP_INITIATOR_PORT);
} else {
cntrlphy_hscb->func_mask = 0;
cntrlphy_hscb->speed_mask = 0;
cntrlphy_hscb->hot_plug_delay = 0;
cntrlphy_hscb->port_type = 0;
}
#ifdef SEQUENCER_UPDATE
cntrlphy_hscb->device_present_timer_ovrd_enable = 0;
cntrlphy_hscb->device_present_timeout_const_override = 0;
#else
cntrlphy_hscb->ovrd_cominit_timer = 0;
cntrlphy_hscb->cominit_timer_const_ovrd = 0;
#endif
memset(&cntrlphy_hscb->res1[0], 0x0, 111);
cntrlphy_hscb->conn_handle = 0xFFFF;
}
/*
* Function:
* asd_hwi_build_abort_task()
*
* Description:
* Build an ABORT TASK SCB.
* ABORT TASK scb is used to abort an SCB previously sent to the
* firmware.
*/
void
asd_hwi_build_abort_task(struct scb *scb, struct scb *scb_to_abort)
{
struct asd_abort_task_hscb *abort_hscb;
struct asd_target *targ;
targ = scb_to_abort->platform_data->targ;
abort_hscb = &scb->hscb->abort_task;
abort_hscb->header.opcode = SCB_ABORT_TASK;
memset(&abort_hscb->protocol_conn_rate, 0x0,
offsetof(struct asd_abort_task_hscb, res3) -
offsetof(struct asd_abort_task_hscb, protocol_conn_rate));
/*
* The conn_rate is only valid when aborting an SCB with SSP protocol.
*/
if (targ->transport_type == ASD_TRANSPORT_SSP)
abort_hscb->protocol_conn_rate = targ->ddb_profile.conn_rate;
if ((SCB_GET_OPCODE(scb_to_abort) == SCB_INITIATE_SSP_TASK) ||
(SCB_GET_OPCODE(scb_to_abort) == SCB_INITIATE_LONG_SSP_TASK))
abort_hscb->protocol_conn_rate |= PROTOCOL_TYPE_SSP;
else if ((SCB_GET_OPCODE(scb_to_abort) == SCB_INITIATE_ATA_TASK) ||
(SCB_GET_OPCODE(scb_to_abort) == SCB_INITIATE_ATAPI_TASK))
abort_hscb->protocol_conn_rate |= PROTOCOL_TYPE_STP;
else
abort_hscb->protocol_conn_rate |= PROTOCOL_TYPE_SMP;
/*
* Build SSP Frame Header and SSP Task IU, these fields only valid
* when aborting an SCB with SSP protocol.
*/
if (targ->transport_type == ASD_TRANSPORT_SSP) {
/* SSP Frame Header. */
abort_hscb->sas_header.frame_type = TASK_FRAME;
memcpy(abort_hscb->sas_header.hashed_dest_sasaddr,
targ->ddb_profile.hashed_sas_addr, HASHED_SAS_ADDR_LEN);
memcpy(abort_hscb->sas_header.hashed_src_sasaddr,
targ->src_port->hashed_sas_addr, HASHED_SAS_ADDR_LEN);
abort_hscb->sas_header.target_port_xfer_tag = 0xFFFF;
abort_hscb->sas_header.data_offset = 0;
/* SSP Task IU. */
if (scb_to_abort->platform_data->dev != NULL) {
/*
* We could be aborting task for SMP target or
* target during discovery and there is no device
* associated with that target.
*/
memcpy(abort_hscb->task_iu.lun,
scb_to_abort->platform_data->dev->saslun,
SAS_LUN_LEN);
}
abort_hscb->task_iu.tmf = ABORT_TASK_TMF;
/*
* Setting tag_to_manage to 0xFFFF will indicate the sequencer
* to use conn_handle, lun, and tc_to_abort to determine the
* I_T_L_Q nexus of the task to be aborted.
*/
abort_hscb->task_iu.tag_to_manage = 0xFFFF;
}
abort_hscb->sister_scb = 0xFFFF;
abort_hscb->conn_handle = targ->ddb_profile.conn_handle;
/*
* For Aborting SSP Task, we need to suspend the data transmission
* of the task to be aborted.
*/
if (SCB_GET_OPCODE(scb_to_abort) == SCB_INITIATE_SSP_TASK) {
abort_hscb->suspend_data = SUSPEND_DATA;
scb->eh_state |= SCB_EH_SUSPEND_SENDQ;
}
abort_hscb->retry_cnt = TASK_RETRY_CNT;
/* Set the TC to be aborted. */
abort_hscb->tc_to_abort = asd_htole16(SCB_GET_INDEX(scb_to_abort));
}
/*
* Function:
* asd_hwi_build_query_task()
*
* Description:
* Build an QUERY TASK SCB.
* QUERY TASK scb is used to issue an SSP Task IU for a Query Task
* Task Management Function.
*/
void
asd_hwi_build_query_task(struct scb *scb, struct scb *scb_to_query)
{
struct asd_query_ssp_task_hscb *query_hscb;
struct asd_target *targ;
targ = scb_to_query->platform_data->targ;
query_hscb = &scb->hscb->query_ssp_task;
query_hscb->header.opcode = SCB_QUERY_SSP_TASK;
memset(&query_hscb->protocol_conn_rate, 0x0,
offsetof(struct asd_query_ssp_task_hscb, res3) -
offsetof(struct asd_query_ssp_task_hscb, protocol_conn_rate));
query_hscb->protocol_conn_rate = (targ->ddb_profile.conn_rate |
PROTOCOL_TYPE_SSP);
/* SSP Frame Header. */
query_hscb->sas_header.frame_type = TASK_FRAME;
memcpy(query_hscb->sas_header.hashed_dest_sasaddr,
targ->ddb_profile.hashed_sas_addr, HASHED_SAS_ADDR_LEN);
memcpy(query_hscb->sas_header.hashed_src_sasaddr,
targ->src_port->hashed_sas_addr, HASHED_SAS_ADDR_LEN);
query_hscb->sas_header.target_port_xfer_tag = 0xFFFF;
query_hscb->sas_header.data_offset = 0;
/* SSP Task IU. */
query_hscb->task_iu.tmf = QUERY_TASK_TMF;
/*
* Setting tag_to_manage to 0xFFFF will indicate the sequencer
* to use conn_handle, lun, and tc_to_query to determine the
* I_T_L_Q nexus of the task to be queried.
*/
query_hscb->task_iu.tag_to_manage = 0xFFFF;
query_hscb->sister_scb = 0xFFFF;
query_hscb->conn_handle = targ->ddb_profile.conn_handle;
query_hscb->retry_cnt = TASK_RETRY_CNT;
/* Set the TC to be queried. */
query_hscb->tc_to_query = asd_htole16(SCB_GET_INDEX(scb_to_query));
}
/*
* Function:
* asd_hwi_build_clear_nexus()
*
* Description:
* Build a CLEAR NEXUS SCB.
* CLEAR NEXUS SCB is used to request the firmware that a set of pending
* transactions pending for a specified nexus be return to the driver
* and free the associated SCBs to the free list.
*/
void
asd_hwi_build_clear_nexus(struct scb *scb, u_int nexus_ind, u_int parm,
u_int context)
{
struct asd_clear_nexus_hscb *clr_nxs_hscb;
struct asd_target *targ;
#define RESUME_SENDQ_REQ \
do { \
if (context == SCB_EH_RESUME_SENDQ) \
clr_nxs_hscb->queue_ind = (uint8_t) RESUME_TX; \
} while (0)
clr_nxs_hscb = &scb->hscb->clear_nexus;
clr_nxs_hscb->header.opcode = SCB_CLEAR_NEXUS;
targ = scb->platform_data->targ;
memset(&clr_nxs_hscb->nexus_ind, 0x0,
offsetof(struct asd_clear_nexus_hscb, res8) -
offsetof(struct asd_clear_nexus_hscb, nexus_ind));
clr_nxs_hscb->nexus_ind = nexus_ind;
switch (nexus_ind) {
case CLR_NXS_I_OR_T:
/* Clear Nexus intended for I or T. */
clr_nxs_hscb->conn_mask_to_clr = targ->src_port->conn_mask;
break;
case CLR_NXS_I_T_L:
/* Clear Nexus intended for I_T_L. */
if (scb->platform_data->dev != NULL) {
memcpy(clr_nxs_hscb->lun_to_clr,
scb->platform_data->dev->saslun,
SAS_LUN_LEN);
}
/* Fallthrough */
case CLR_NXS_IT_OR_TI:
/* Clear Nexus intended for I_T or T_I. */
clr_nxs_hscb->conn_handle_to_clr =
targ->ddb_profile.conn_handle;
clr_nxs_hscb->queue_ind = (uint8_t) parm;
RESUME_SENDQ_REQ;
break;
case CLR_NXS_I_T_L_Q_TAG:
/* Clear Nexus intended for I_T_L_Q (by tag). */
clr_nxs_hscb->tag_to_clr = (uint16_t) parm;
clr_nxs_hscb->conn_handle_to_clr =
targ->ddb_profile.conn_handle;
if (scb->platform_data->dev != NULL) {
memcpy(clr_nxs_hscb->lun_to_clr,
scb->platform_data->dev->saslun,
SAS_LUN_LEN);
}
RESUME_SENDQ_REQ;
break;
case CLR_NXS_I_T_L_Q_TC:
/* Clear Nexus intended for I_T_L_Q (by TC). */
clr_nxs_hscb->tc_to_clr = (uint16_t) parm;
clr_nxs_hscb->conn_handle_to_clr =
targ->ddb_profile.conn_handle;
if (scb->platform_data->dev != NULL) {
memcpy(clr_nxs_hscb->lun_to_clr,
scb->platform_data->dev->saslun,
SAS_LUN_LEN);
}
RESUME_SENDQ_REQ;
break;
case CLR_NXS_I_T_L_Q_STAG:
/* Clear Nexus intended for I_T_L_Q (by SATA tag). */
clr_nxs_hscb->conn_handle_to_clr =
targ->ddb_profile.conn_handle;
/*
* Bits 4-0 of the tag_to_clr contain the SATA tag to be
* cleared. Bits 15-5 shall be set to zero.
*/
clr_nxs_hscb->tag_to_clr = ((uint16_t) parm && 0x001F);
RESUME_SENDQ_REQ;
break;
case CLR_NXS_ADAPTER:
/* Clear Nexus for Adapter. */
default:
/* Unsupported Clear Nexus function. */
break;
}
clr_nxs_hscb->nexus_ctx = (uint16_t) context;
}
/*
* Function:
* asd_hwi_build_ssp_tmf()
*
* Description:
* Build a SSP TMF SCB.
* SSP TMF SCB is used to issue an SSP Task information unit for a
* LOGICAL UNIT RESET, ABORT TASK SET, CLEAR TASK SET, or CLEAR ACA
* task management function.
*/
void
asd_hwi_build_ssp_tmf(struct scb *scb, struct asd_target *targ,
uint8_t *lun, u_int tmf_opcode)
{
struct asd_ssp_tmf_hscb *tmf_hscb;
tmf_hscb = &scb->hscb->ssp_tmf;
tmf_hscb->header.opcode = SCB_INITIATE_SSP_TMF;
memset(&tmf_hscb->protocol_conn_rate, 0x0,
offsetof(struct asd_ssp_tmf_hscb, res3) -
offsetof(struct asd_ssp_tmf_hscb, protocol_conn_rate));
tmf_hscb->protocol_conn_rate = (targ->ddb_profile.conn_rate |
PROTOCOL_TYPE_SSP);
/* SSP Frame Header. */
tmf_hscb->sas_header.frame_type = TASK_FRAME;
memcpy(tmf_hscb->sas_header.hashed_dest_sasaddr,
targ->ddb_profile.hashed_sas_addr, HASHED_SAS_ADDR_LEN);
memcpy(tmf_hscb->sas_header.hashed_src_sasaddr,
targ->src_port->hashed_sas_addr, HASHED_SAS_ADDR_LEN);
tmf_hscb->sas_header.target_port_xfer_tag = 0xFFFF;
tmf_hscb->sas_header.data_offset = 0;
/* SSP Task IU. */
memcpy(tmf_hscb->task_iu.lun, lun, SAS_LUN_LEN);
tmf_hscb->task_iu.tmf = tmf_opcode;
tmf_hscb->sister_scb = 0xFFFF;
tmf_hscb->conn_handle = targ->ddb_profile.conn_handle;
/* Suspend data transmission to the target. */
scb->eh_state |= SCB_EH_SUSPEND_SENDQ;
tmf_hscb->suspend_data = SUSPEND_DATA;
tmf_hscb->retry_cnt = TASK_RETRY_CNT;
}
/*
* Function:
* asd_hwi_build_smp_phy_req()
*
* Description:
* Build a SMP PHY related request.
*/
static void
asd_hwi_build_smp_phy_req(struct asd_port *port, int req_type,
int phy_id, int ctx)
{
struct SMPRequest *smp_req;
smp_req = port->dc.SMPRequestFrame;
memset(smp_req, 0, sizeof(*smp_req));
smp_req->SMPFrameType = SMP_REQUEST_FRAME;
switch (req_type) {
case PHY_CONTROL:
smp_req->Function = PHY_CONTROL;
smp_req->Request.PhyControl.PhyIdentifier = phy_id;
smp_req->Request.PhyControl.PhyOperation = ctx;
break;
case REPORT_PHY_ERROR_LOG:
smp_req->Function = REPORT_PHY_ERROR_LOG;
smp_req->Request.ReportPhyErrorLog.PhyIdentifier = phy_id;
break;
default:
panic("Unknown SMP PHY request type.\n");
break;
}
/*
* DC: Currently, we are not changing the programmed min/max
* physical link rate for LINK RESET or HARD RESET.
* We might need to change the link rate if CMSI application
* required..
*/
}
/*
* Function:
* asd_hwi_build_smp_task()
*
* Description:
* Build a SMP TASK SCB.
* SMP TASK SCB is used to send an SMP TASK to an expander.
*/
void
asd_hwi_build_smp_task(struct scb *scb, struct asd_target *targ,
uint64_t req_bus_addr, u_int req_len,
uint64_t resp_bus_addr, u_int resp_len)
{
struct asd_smp_task_hscb *smp_hscb;
smp_hscb = &scb->hscb->smp_task;
smp_hscb->header.opcode = SCB_INITIATE_SMP_TASK;
memset(&smp_hscb->protocol_conn_rate, 0x0,
offsetof(struct asd_smp_task_hscb, res5) -
offsetof(struct asd_ssp_tmf_hscb, protocol_conn_rate));
smp_hscb->protocol_conn_rate = (targ->ddb_profile.conn_rate |
PROTOCOL_TYPE_SMP);
smp_hscb->smp_req_busaddr = req_bus_addr;
smp_hscb->smp_req_size = req_len;
smp_hscb->smp_req_ds = 0;
smp_hscb->sister_scb = 0xffff;
smp_hscb->conn_handle = targ->ddb_profile.conn_handle;
smp_hscb->smp_resp_busaddr = resp_bus_addr;
smp_hscb->smp_resp_size = resp_len;
smp_hscb->smp_resp_ds = 0;
}
/*
* Function:
* asd_hwi_build_ssp_task()
*
* Description:
* Build a SSP TASK SCB.
* SSP TASK SCB is used to send an SSP TASK to an expander.
*/
void
asd_hwi_build_ssp_task(struct scb *scb, struct asd_target *targ,
uint8_t *saslun, uint8_t *cdb, uint32_t cdb_len,
uint8_t addl_cdb_len, uint32_t data_len)
{
struct asd_ssp_task_hscb *ssp_hscb;
ssp_hscb = &scb->hscb->ssp_task;
ssp_hscb->header.opcode = SCB_INITIATE_SSP_TASK;
ssp_hscb->protocol_conn_rate = targ->ddb_profile.conn_rate
| PROTOCOL_TYPE_SSP;
ssp_hscb->xfer_len = asd_htole32(data_len);
ssp_hscb->sas_header.frame_type = OPEN_ADDR_FRAME;
memcpy(ssp_hscb->sas_header.hashed_dest_sasaddr,
targ->ddb_profile.hashed_sas_addr, HASHED_SAS_ADDR_LEN);
ssp_hscb->sas_header.res = 0;
memcpy(ssp_hscb->sas_header.hashed_src_sasaddr,
targ->src_port->hashed_sas_addr, HASHED_SAS_ADDR_LEN);
memset(ssp_hscb->sas_header.res1, 0,
offsetof(struct asd_sas_header, target_port_xfer_tag) -
offsetof(struct asd_sas_header, res1));
ssp_hscb->sas_header.target_port_xfer_tag = 0xFFFF;
ssp_hscb->sas_header.data_offset = 0;
/* SSP Command IU */
memset(ssp_hscb->lun, 0,
offsetof(struct asd_ssp_task_hscb, cdb) -
offsetof(struct asd_ssp_task_hscb, lun));
memcpy(ssp_hscb->lun, saslun, 8);
memcpy(ssp_hscb->cdb, cdb, cdb_len);
memset(&ssp_hscb->cdb[cdb_len], 0,
SCB_EMBEDDED_CDB_SIZE - cdb_len);
ssp_hscb->addl_cdb_len = addl_cdb_len;
ssp_hscb->sister_scb = 0xFFFF;
ssp_hscb->conn_handle = targ->ddb_profile.conn_handle;
ssp_hscb->retry_cnt = TASK_RETRY_CNT;
memset(&ssp_hscb->LAST_SSP_HSCB_FIELD, 0,
offsetof(struct asd_ssp_task_hscb, sg_elements) -
offsetof(struct asd_ssp_task_hscb, LAST_SSP_HSCB_FIELD));
return;
}
/*
* Function:
* asd_hwi_build_stp_task()
*
* Description:
* Build a STP TASK SCB.
* STP TASK SCB is used to send an ATA TASK to an expander.
*/
void
asd_hwi_build_stp_task(struct scb *scb, struct asd_target *targ,
uint32_t data_len)
{
struct asd_ata_task_hscb *ata_hscb;
ata_hscb = &scb->hscb->ata_task;
ata_hscb->header.opcode = SCB_INITIATE_ATA_TASK;
ata_hscb->protocol_conn_rate =
PROTOCOL_TYPE_SATA | targ->ddb_profile.conn_rate;
ata_hscb->xfer_len = asd_htole32(data_len);
ata_hscb->data_offset = 0;
ata_hscb->sister_scb = 0xffff;
ata_hscb->conn_handle = targ->ddb_profile.conn_handle;
ata_hscb->retry_cnt = TASK_RETRY_CNT;
ata_hscb->affiliation_policy = 0;
ata_hscb->ata_flags = 0;
#ifdef SEQUENCER_UPDATE
ata_hscb->ata_flags |= UNTAGGED;
#else
#ifdef TAGGED_QUEUING
// RST - add support for SATA II queueing
ata_hscb->ata_flags |= LEGACY_QUEUING;
#else
ata_hscb->ata_flags |= UNTAGGED;
#endif
#endif
return;
}
/*
* Function:
* asd_hwi_hash()
*
* Desctiption:
* Convert a 64-bit SAS address into a 24-bit Hash address.
* This is based on the hash implementation from the SAS 1.1 draft.
*/
void
asd_hwi_hash(uint8_t *sas_addr, uint8_t *hashed_addr)
{
const uint32_t distance_9_poly = 0x01DB2777;
uint32_t upperbits;
uint32_t lowerbits;
uint32_t msb;
uint32_t moving_one;
uint32_t leading_bit;
uint32_t regg;
int i;
upperbits = scsi_4btoul(sas_addr);
lowerbits = scsi_4btoul(sas_addr + 4);
msb = 0x01000000;
regg = 0;
moving_one = 0x80000000;
for (i = 31; i >= 0; i--) {
leading_bit = 0;
if (moving_one & upperbits)
leading_bit = msb;
regg <<= 1;
regg ^= leading_bit;
if (regg & msb)
regg ^= distance_9_poly;
moving_one >>= 1;
}
moving_one = 0x80000000;
for (i = 31; i >= 0; i--) {
leading_bit = 0;
if (moving_one & lowerbits)
leading_bit = msb;
regg <<= 1;
regg ^= leading_bit;
if (regg & msb)
regg ^= distance_9_poly;
moving_one >>= 1;
}
scsi_ulto3b(regg, hashed_addr);
}
/*************************** Error Handling routines **************************/
void
asd_recover_cmds(struct asd_softc *asd)
{
struct scb *scb;
struct scb *free_scb;
struct scb *safe_scb;
u_long flags;
Scsi_Cmnd *cmd;
struct asd_device *dev;
if (list_empty(&asd->timedout_scbs)) {
asd_log(ASD_DBG_ERROR, "Timed-out scbs already completed.\n");
goto exit;
}
list_for_each_entry_safe(scb, safe_scb, &asd->timedout_scbs,
timedout_links) {
asd_lock(asd, &flags);
#ifdef ASD_DEBUG
asd_log(ASD_DBG_ERROR, "asd_recover_cmds: Curr State: 0x%x Status: 0x%x.\n",
scb->eh_state, scb->eh_status);
#endif
/*
* Error recovery is in progress for this scb.
* Proceed to next one.
*/
if ((scb->eh_state & SCB_EH_IN_PROGRESS) != 0) {
asd_unlock(asd, &flags);
continue;
}
/*
* Error recovery is completed for this scb.
*/
if (scb->eh_state == SCB_EH_DONE) {
asd_unlock(asd, &flags);
goto done;
}
/*
* Only allowed one Error Recovery ongoing for a particular
* target.
*/
if ((scb->platform_data->targ->flags &
ASD_TARG_IN_RECOVERY) != 0) {
asd_unlock(asd, &flags);
continue;
}
/*
* Acquire a free SCB from reserved pool to be used
* for error recovery purpose.
*/
if ((free_scb = asd_hwi_get_scb(asd, 1)) == NULL) {
asd_log(ASD_DBG_ERROR, "Failed to get free SCB "
"for error recovery.\n");
asd_unlock(asd, &flags);
continue;
}
/* Mark this target to be in recovery mode. */
scb->platform_data->targ->flags |= ASD_TARG_IN_RECOVERY;
/* Freeze the target's queue. */
asd_freeze_targetq(asd, scb->platform_data->targ);
/* Initialiaze the state. */
scb->eh_state |= SCB_EH_IN_PROGRESS;
free_scb->eh_state = SCB_EH_INITIATED;
free_scb->eh_status = SCB_EH_SUCCEED;
switch (scb->eh_state & SCB_EH_LEVEL_MASK) {
case SCB_EH_ABORT_REQ:
asd_log(ASD_DBG_ERROR, "ABORT ER REQ.\n");
asd_hwi_abort_scb(asd, scb, free_scb);
break;
case SCB_EH_LU_RESET_REQ:
asd_log(ASD_DBG_ERROR, "LU RESET ER REQ.\n");
asd_hwi_reset_lu(asd, scb, free_scb);
break;
case SCB_EH_DEV_RESET_REQ:
asd_log(ASD_DBG_ERROR, "DEV RESET ER REQ.\n");
asd_hwi_reset_device(asd, scb, free_scb);
break;
case SCB_EH_PORT_RESET_REQ:
asd_log(ASD_DBG_ERROR, "PORT RESET ER REQ.\n");
asd_hwi_reset_port(asd, scb, free_scb);
break;
case SCB_EH_RESUME_SENDQ:
{
struct asd_port *port;
asd_log(ASD_DBG_ERROR, "RESUME SENDQ REQ.\n");
asd_unlock(asd, &flags);
port = SCB_GET_SRC_PORT(scb);
asd_delay(2000000); //wait 2 sec for Broadcast event
asd_lock(asd, &flags);
asd_hwi_resume_sendq(asd, scb, free_scb);
break;
}
default:
asd_log(ASD_DBG_ERROR, "Unknown Error Recovery "
"Level scb 0x%x.\n",scb);
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
break;
}
asd_unlock(asd, &flags);
done:
if (scb->eh_state == SCB_EH_DONE) {
/*
* Error recovery is done for this scb,
* Clean up and free the scb.
*/
asd_lock(asd, &flags);
list_del(&scb->timedout_links);
scb->platform_data->targ->flags &=
~ASD_TARG_IN_RECOVERY;
/* Unfreeze the target's queue. */
asd_unfreeze_targetq(asd, scb->platform_data->targ);
scb->eh_status =SCB_EH_SUCCEED;
scb->eh_post(asd, scb);
if(scb->flags & SCB_ABORT_DONE)
{
scb->eh_status =SCB_EH_SUCCEED;
}
else
{
scb->eh_status =SCB_EH_FAILED;
}
if (scb->eh_status != SCB_EH_FAILED) {
struct asd_device *dev;
/*
* Schedule a timer to run the device
* queue if the device is not frozen and
* not in the process of being removed.
*/
dev = scb->platform_data->dev;
if ((dev != NULL) && (dev->qfrozen == 0) &&
(dev->flags & ASD_DEV_TIMER_ACTIVE) == 0 &&
(dev->target->flags &
ASD_TARG_HOT_REMOVED) == 0) {
asd_setup_dev_timer(
dev, HZ,
asd_timed_run_dev_queue);
}
/*
* Only free the scb if the error recovery is
* successful.
*/
scb->flags &= ~(SCB_TIMEDOUT+SCB_ABORT_DONE);
asd_hwi_free_scb(asd, scb);
} // if (scb->eh_status != SCB_EH_FAILED)
//JDTEST
else
{
//cleaning up failed recovery scb
asd_log(ASD_DBG_ERROR, "scb 0x%x SCB_EH_FAILED flags 0x%x\n",scb, scb->flags);
dev = scb->platform_data->dev;
if ((dev != NULL) && (dev->qfrozen == 0) &&
(dev->flags & ASD_DEV_TIMER_ACTIVE) == 0 &&
(dev->target->flags &
ASD_TARG_HOT_REMOVED) == 0) {
asd_setup_dev_timer(
dev, HZ,
asd_timed_run_dev_queue);
}
if(scb->flags & SCB_PENDING)
{
list_del(&scb->hwi_links);
}
if(scb->flags & SCB_INTERNAL)
{
list_del(&scb->owner_links);
asd_hwi_free_scb(asd, scb);
}
else
{
asd_log(ASD_DBG_INFO,"free scb from pending queue\n");
list_del(&scb->owner_links);
cmd = &acmd_scsi_cmd(scb->io_ctx);
dev = scb->platform_data->dev;
dev->active--;
dev->openings++;
if ((scb->flags & SCB_DEV_QFRZN) != 0) {
scb->flags &= ~SCB_DEV_QFRZN;
dev->qfrozen--;
}
asd_unmap_scb(asd, scb);
#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
asd_cmd_set_host_status(cmd, DID_NO_CONNECT);
#else
asd_cmd_set_offline_status(cmd);
#endif
cmd->scsi_done(cmd);
asd_hwi_free_scb(asd, scb);
} //if(scb->flags & SCB_INTERNAL)
} //if (scb->eh_status != SCB_EH_FAILED)
asd_unlock(asd, &flags);
} //if (scb->eh_state == SCB_EH_DONE)
}//list_for_each_entry_safe(scb, safe_scb, &asd->timedout_scbs,
exit:
return;
}
static void
asd_scb_eh_timeout(u_long arg)
{
struct asd_softc *asd;
struct scb *scb;
struct scb *err_scb;
u_long flags;
scb = (struct scb *) arg;
err_scb = (struct scb *) scb->post_stack[0].io_ctx;
asd = scb->softc;
asd_lock(asd, &flags);
scb->eh_state = SCB_EH_TIMEDOUT;
err_scb->eh_state &= ~SCB_EH_IN_PROGRESS;
/*
* Error recovery SCB timed out.
* If this error recovery requested by the OS, we need to mark the
* error recovery failed and make an attempt to perform the next
* level error recovery if possible.
*/
#ifdef ASD_DEBUG
//JD
asd_log(ASD_DBG_INFO, "asd_scb_eh_timeout: err_scb->eh_state 0x%x\n",err_scb->eh_state);
#endif
switch (err_scb->eh_state) {
case SCB_EH_ABORT_REQ:
err_scb->eh_state = SCB_EH_LU_RESET_REQ;
break;
case SCB_EH_LU_RESET_REQ:
err_scb->eh_state = SCB_EH_DEV_RESET_REQ;
break;
case SCB_EH_DEV_RESET_REQ:
err_scb->eh_state = SCB_EH_PORT_RESET_REQ;
break;
case SCB_EH_PORT_RESET_REQ:
{
// scb timeout during reset port
struct asd_port *port;
struct asd_target *targ;
port = SCB_GET_SRC_PORT(err_scb);
/* Unfreeze all the targets. */
list_for_each_entry(targ, &port->targets, all_domain_targets) {
targ->qfrozen--;
asd_log(ASD_DBG_INFO,"clear freezen in timeout ptr=%p num=%d\n",targ,targ->qfrozen);
}
}
default:
/*
* Currently, our biggest hammer now is PORT RESET.
* We might perform ADAPTER RESET later on.
*/
err_scb->eh_state = SCB_EH_DONE;
break;
}
err_scb->eh_status = SCB_EH_FAILED;
err_scb->platform_data->targ->flags &= ~ASD_TARG_IN_RECOVERY;
asd_unlock(asd, &flags);
asd_wakeup_sem(&asd->platform_data->ehandler_sem);
}
int
asd_hwi_check_cmd_pending(struct asd_softc *asd, struct scb *scb,
struct asd_done_list *dl)
{
struct scb *abort_scb;
while (!list_empty(&asd->timedout_scbs)) {
abort_scb = list_entry(asd->timedout_scbs.next,
struct scb, timedout_links);
if (((struct asd_abort_task_hscb *)
&scb->hscb->abort_task)->tc_to_abort ==
asd_htole16(SCB_GET_INDEX(abort_scb))) {
return (1);
}
}
return (0);
}
/*
* Function:
* asd_hwi_abort_scb()
*
* Description:
* This routine will issue an ABORT_TASK to abort the requested scb.
* ONLY SCB with protocol SSP, SMP and STP can be issued ABORT_TASK TMF.
*/
static void
asd_hwi_abort_scb(struct asd_softc *asd, struct scb *scb_to_abort,
struct scb *scb)
{
ASD_LOCK_ASSERT(asd);
asd_log(ASD_DBG_ERROR, "Curr State: 0x%x Status: 0x%x.\n",
scb->eh_state, scb->eh_status);
/*
* DC: We probably need to search the scb_to_abort in the
* target/device queue as initial step for internal requested
* command.
*/
switch (scb->eh_state) {
case SCB_EH_INITIATED:
{
/*
* Validate the opcode of scb to be aborted.
* Only scb with specific opcode can be aborted.
*/
if ((SCB_GET_OPCODE(scb_to_abort) != SCB_INITIATE_SSP_TASK) &&
(SCB_GET_OPCODE(scb_to_abort) != SCB_INITIATE_SMP_TASK) &&
(SCB_GET_OPCODE(scb_to_abort) !=
SCB_INITIATE_LONG_SSP_TASK) &&
(SCB_GET_OPCODE(scb_to_abort) != SCB_INITIATE_ATA_TASK) &&
(SCB_GET_OPCODE(scb_to_abort) != SCB_INITIATE_ATAPI_TASK)) {
asd_log(ASD_DBG_ERROR, "Requested to abort unsupported "
"SCB request.\n");
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
/*
* Recursively call this function again upon changing
* the state.
*/
asd_hwi_abort_scb(asd, scb_to_abort, scb);
break;
}
scb->platform_data->targ = scb_to_abort->platform_data->targ;
scb->platform_data->dev = scb_to_abort->platform_data->dev;
scb->eh_state = SCB_EH_ABORT_REQ;
asd_hwi_abort_scb(asd, (struct scb *) scb_to_abort, scb);
break;
}
case SCB_EH_ABORT_REQ:
/* Build the ABORT_TASK SCB. */
asd_hwi_build_abort_task(scb, scb_to_abort);
scb->flags |= (SCB_INTERNAL | SCB_ACTIVE | SCB_RECOVERY);
asd_setup_scb_timer(scb, (4 * HZ), asd_scb_eh_timeout);
//JD
#ifdef ASD_DEBUG
asd_log(ASD_DBG_INFO, "Prepare to abort scb index(TC): 0x%x, TAG(0x%x) cmd LBA 0x%02x%02x%02x%02x - 0x%02x%02x\n",
SCB_GET_INDEX(scb_to_abort), SCB_GET_SSP_TAG(scb_to_abort),
scb_to_abort->io_ctx->scsi_cmd.cmnd[2],
scb_to_abort->io_ctx->scsi_cmd.cmnd[3],
scb_to_abort->io_ctx->scsi_cmd.cmnd[4],
scb_to_abort->io_ctx->scsi_cmd.cmnd[5],
scb_to_abort->io_ctx->scsi_cmd.cmnd[7],
scb_to_abort->io_ctx->scsi_cmd.cmnd[8]);
#endif
asd_push_post_stack(asd, scb, (void *) scb_to_abort,
asd_hwi_abort_scb_done);
/* Post the ABORT_TASK SCB. */
asd_hwi_post_scb(asd, scb);
break;
case SCB_EH_CLR_NXS_REQ:
/*
* The Clear Nexus SCB has been prepared in the abort
* post routine. All we need is to post it to the firmware.
*/
scb->flags |= (SCB_INTERNAL | SCB_ACTIVE | SCB_RECOVERY);
asd_setup_scb_timer(scb, (4 * HZ), asd_scb_eh_timeout);
asd_push_post_stack(asd, scb, (void *) scb_to_abort,
asd_hwi_abort_scb_done);
asd_hwi_post_scb(asd, scb);
break;
case SCB_EH_RESUME_SENDQ:
/*
* We are here because the ABORT TMF failed.
* We need to resume the data transmission of the task
* that was going to be aborted.
*/
scb->flags |= (SCB_INTERNAL | SCB_ACTIVE | SCB_RECOVERY);
asd_hwi_build_clear_nexus(scb, CLR_NXS_I_T_L_Q_TC,
SCB_GET_INDEX(scb_to_abort),
SCB_EH_RESUME_SENDQ);
asd_setup_scb_timer(scb, (4 * HZ), asd_scb_eh_timeout);
asd_push_post_stack(asd, scb, (void *) scb_to_abort,
asd_hwi_abort_scb_done);
asd_hwi_post_scb(asd, scb);
break;
case SCB_EH_DONE:
scb_to_abort->eh_state = scb->eh_state;
scb_to_abort->eh_status = scb->eh_status;
if ((scb_to_abort->eh_state == SCB_EH_DONE) &&
(scb_to_abort->eh_status == SCB_EH_FAILED)) {
/*
* Failed to perform abort error recovery for the
* failed command, we shall procced with the next
* level of error recovery (Logical Unit Reset).
* We need to change the scb eh_state to
* SCB_EH_LU_RESET_REQ.
*/
//JD
#ifdef ASD_DEBUG
asd_log(ASD_DBG_INFO, "asd_hwi_abort_scb failed to perform scb index(TC): 0x%x, TAG(0x%x), cmd LBA 0x%02x%02x%02x%02x - 0x%02x%02x, going to reset all.\n",
SCB_GET_INDEX(scb_to_abort), SCB_GET_SSP_TAG(scb_to_abort),
scb_to_abort->io_ctx->scsi_cmd.cmnd[2],
scb_to_abort->io_ctx->scsi_cmd.cmnd[3],
scb_to_abort->io_ctx->scsi_cmd.cmnd[4],
scb_to_abort->io_ctx->scsi_cmd.cmnd[5],
scb_to_abort->io_ctx->scsi_cmd.cmnd[7],
scb_to_abort->io_ctx->scsi_cmd.cmnd[8]);
#ifdef DEBUG_DDB
{
u_long lseqs_to_dump;
u_int lseq_id;
int indx;
for(indx=0;indx< asd->ddb_bitmap_size; indx++)
{
lseq_id = 0;
lseqs_to_dump = asd->free_ddb_bitmap[indx];
while (lseqs_to_dump != 0) {
for ( ; lseq_id < (8 * sizeof(u_long)); lseq_id++) {
if (lseqs_to_dump & (1UL << lseq_id)) {
lseqs_to_dump &= ~(1UL << lseq_id);
break;
}
}
/* Dump out specific LSEQ Registers state. */
asd_hwi_dump_ssp_smp_ddb_site(asd, lseq_id + (indx * 8 * sizeof(ulong)));
}
}
}
asd_hwi_dump_seq_state(asd, asd->hw_profile.enabled_phys);
#endif
#endif
scb_to_abort->eh_state = SCB_EH_LU_RESET_REQ;
scb_to_abort->platform_data->targ->flags &=
~ASD_TARG_IN_RECOVERY;
}
asd_hwi_free_scb(asd, scb);
asd_wakeup_sem(&asd->platform_data->ehandler_sem);
break;
default:
asd_log(ASD_DBG_ERROR, "Invalid EH State 0x%x.\n",
scb->eh_state);
scb_to_abort->eh_state = SCB_EH_DONE;
scb_to_abort->eh_status = SCB_EH_FAILED;
asd_hwi_free_scb(asd, scb);
asd_wakeup_sem(&asd->platform_data->ehandler_sem);
break;
}
}
static void
asd_hwi_abort_scb_done(struct asd_softc *asd, struct scb *scb,
struct asd_done_list *dl)
{
struct scb *scb_to_abort;
//JD
#ifdef ASD_DEBUG
asd_log(ASD_DBG_INFO, "asd_hwi_abort_scb_done: scb index(TC): 0x%x, TAG(0x%x), cmd LBA 0x%02x%02x%02x%02x - 0x%02x%02x is done\n",
SCB_GET_INDEX(scb), SCB_GET_SSP_TAG(scb),
scb->io_ctx->scsi_cmd.cmnd[2],
scb->io_ctx->scsi_cmd.cmnd[3],
scb->io_ctx->scsi_cmd.cmnd[4],
scb->io_ctx->scsi_cmd.cmnd[5],
scb->io_ctx->scsi_cmd.cmnd[7],
scb->io_ctx->scsi_cmd.cmnd[8]);
asd_log(ASD_DBG_INFO, "asd_hwi_abort_scb_done: scb ptr=%p scb_abort ptr=%p\n",scb,scb->io_ctx);
#endif
/*
* There is a possibility that this post routine is called after
* the SCB timedout. So, only delete the timer if the SCB hasn't
* timedout.
*/
if (scb->eh_state != SCB_EH_TIMEDOUT)
del_timer_sync(&scb->platform_data->timeout);
/*
* This post routine is shared by ABORT_TASK and CLEAR_NEXUS
* issued by this abort handler code.
* Hence, the DL opcodes also apply to both SCB task.
*/
switch (dl->opcode) {
case TASK_COMP_WO_ERR:
case TMF_F_W_TAG_NOT_FOUND:
case TMF_F_W_CONN_HNDL_NOT_FOUND:
case TMF_F_W_TASK_ALREADY_DONE:
case TMF_F_W_TAG_ALREADY_FREE:
case TMF_F_W_TC_NOT_FOUND:
/*
* For SMP or STP target, firmware will only try to abort
* the task if it is still in its execution queue.
* If the task to be aborted couldn't be found, mostly like it
* has been issued to the target.
* We should try next level error recovery.
*/
scb_to_abort=(struct scb *)scb->io_ctx;
asd_log(ASD_DBG_INFO, "protocol type=%x flags=%x \n",
scb->platform_data->targ->device_protocol_type,scb_to_abort->flags);
if (scb->platform_data->targ->device_protocol_type
!= ASD_DEVICE_PROTOCOL_SCSI) {
if(!(scb_to_abort->flags & SCB_ABORT_DONE))
{
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
break;
}
}
/* Fall thru */
case TASK_ABORTED_BY_ITNL_EXP:
/* Indicate that Abort succeeded. */
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_SUCCEED;
break;
case TASK_F_W_NAK_RCVD:
/*
* Indicate that Abort failed.
* If this is a failure in issuing ABORT TMF, we need to
* resume the data transmission of the task that was
* going to be aborted.
*/
if ((scb->eh_state & SCB_EH_SUSPEND_SENDQ) != 0)
scb->eh_state = SCB_EH_RESUME_SENDQ;
else
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
break;
case SSP_TASK_COMP_W_RESP:
{
union edb *edb;
struct scb *escb;
struct ssp_resp_edb *redb;
struct ssp_resp_iu *riu;
u_int edb_index;
edb = asd_hwi_get_edb_from_dl(asd, scb, dl, &escb, &edb_index);
if (edb == NULL) {
asd_log(ASD_DBG_ERROR, "Invalid EDB recv for SSP "
"comp w/response.\n");
scb->eh_state = SCB_EH_RESUME_SENDQ;
scb->eh_status = SCB_EH_SUCCEED;
break;
}
/*
* Search if the aborted command still pending on the firmware
* queue. If so, we need to send CLEAR_NEXUS to have the
* command freed and returned to us.
*/
if (!asd_hwi_check_cmd_pending(asd, scb, dl)) {
asd_log(ASD_DBG_RUNTIME, "Aborted cmd has been "
"completed.\n");
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_SUCCEED;
asd_hwi_free_edb(asd, escb, edb_index);
break;
}
redb = &edb->ssp_resp;
riu = &redb->resp_frame.riu;
if (SSP_RIU_DATAPRES(riu) == SSP_RIU_DATAPRES_RESP) {
uint8_t resp_code;
resp_code = ((struct resp_data_iu *)
&riu->data[0])->resp_code;
/* Handle the SSP TMF response code. */
asd_hwi_map_tmf_resp(scb, resp_code);
if (scb->eh_state == SCB_EH_CLR_NXS_REQ) {
asd_log(ASD_DBG_ERROR,
"Tag to Clear=0x%x.\n",
asd_be16toh(redb->tag_to_clear));
/*
* Upon receving TMF_COMPLETE, we need to send
* CLEAR_NEXUS SCB for tag_to_clear.
*/
asd_hwi_build_clear_nexus(scb,
CLR_NXS_I_T_L_Q_TAG,
redb->tag_to_clear,
/*ctx*/0);
}
} else {
/*
* Response Data not available. Protocol error.
* Indicate that Abort failed.
*/
scb->eh_state = SCB_EH_RESUME_SENDQ;
scb->eh_status = SCB_EH_FAILED;
}
asd_hwi_free_edb(asd, escb, edb_index);
break;
}
case TASK_F_W_OPEN_REJECT:
scb->eh_state = SCB_EH_RESUME_SENDQ;
scb->eh_status = SCB_EH_FAILED;
break;
case RESUME_COMPLETE:
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
break;
case TASK_CLEARED:
/*
* Previous error recovery SCB that timed-out and
* was aborted.
* All we need to do here is just free the scb.
*/
asd_hwi_free_scb(asd, scb);
return;
default:
asd_log(ASD_DBG_ERROR, "DL opcode not handled.\n");
scb->eh_state = SCB_EH_RESUME_SENDQ;
scb->eh_status = SCB_EH_FAILED;
break;
}
asd_hwi_abort_scb(asd, (struct scb *) scb->io_ctx, scb);
}
/*
* Function:
* asd_hwi_reset_lu()
*
* Description:
* Issue a Logical Unit Reset to the end device.
* LU Reset can only be done for SSP end device.
*/
static void
asd_hwi_reset_lu(struct asd_softc *asd, struct scb *scb_to_reset,
struct scb *scb)
{
ASD_LOCK_ASSERT(asd);
asd_log(ASD_DBG_ERROR, "Curr State: 0x%x Status: 0x%x.\n",
scb->eh_state, scb->eh_status);
switch (scb->eh_state) {
case SCB_EH_INITIATED:
{
struct asd_target *targ;
struct asd_device *dev;
targ = scb_to_reset->platform_data->targ;
dev = scb_to_reset->platform_data->dev;
if ((targ == NULL) || (dev == NULL)) {
/* This shouldn't happen. */
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
asd_hwi_reset_lu(asd, scb_to_reset, scb);
break;
}
/*
* Only SSP end device can be issued a LU reset.
*/
if (targ->device_protocol_type != ASD_DEVICE_PROTOCOL_SCSI) {
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
asd_hwi_reset_lu(asd, (struct scb *) scb_to_reset, scb);
break;
}
scb->platform_data->targ = targ;
scb->platform_data->dev = dev;
scb->eh_state = SCB_EH_LU_RESET_REQ;
asd_hwi_reset_lu(asd, (struct scb *) scb_to_reset, scb);
break;
}
case SCB_EH_LU_RESET_REQ:
/* Build LUR Task Management Function. */
asd_hwi_build_ssp_tmf(scb, scb->platform_data->targ,
scb->platform_data->dev->saslun,
LOGICAL_UNIT_RESET_TMF);
scb->flags |= (SCB_INTERNAL | SCB_ACTIVE | SCB_RECOVERY);
asd_setup_scb_timer(scb, (4 * HZ), asd_scb_eh_timeout);
asd_push_post_stack(asd, scb, (void *) scb_to_reset,
asd_hwi_reset_lu_done);
asd_hwi_post_scb(asd, scb);
break;
case SCB_EH_CLR_NXS_REQ:
asd_hwi_build_clear_nexus(scb, CLR_NXS_I_T_L,
(RESUME_TX | NOT_IN_Q | SEND_Q),
/*ctx*/0);
scb->flags |= (SCB_INTERNAL | SCB_ACTIVE | SCB_RECOVERY);
asd_setup_scb_timer(scb, (4 * HZ), asd_scb_eh_timeout);
asd_push_post_stack(asd, scb, (void *) scb_to_reset,
asd_hwi_reset_lu_done);
asd_hwi_post_scb(asd, scb);
break;
case SCB_EH_RESUME_SENDQ:
/*
* If we failed to perform LU Reset, we need to resume
* the firmware send queue for the I_T_L.
*/
asd_hwi_build_clear_nexus(scb, CLR_NXS_I_T_L,
RESUME_TX, /*ctx*/0);
scb->flags |= (SCB_INTERNAL | SCB_ACTIVE | SCB_RECOVERY);
asd_setup_scb_timer(scb, (4 * HZ), asd_scb_eh_timeout);
asd_push_post_stack(asd, scb, (void *) scb_to_reset,
asd_hwi_reset_lu_done);
asd_hwi_post_scb(asd, scb);
break;
case SCB_EH_DONE:
{
scb_to_reset->eh_state = scb->eh_state;
scb_to_reset->eh_status = scb->eh_status;
if ((scb_to_reset->eh_state == SCB_EH_DONE) &&
(scb_to_reset->eh_status == SCB_EH_FAILED)) {
/*
* Failed to perform LU Reset or LU Reset is not
* supported then we shall procced with
* the next level of error recovery (Device Port Reset).
* We need to change the scb eh_state to
* SCB_EH_DEV_RESET_REQ.
*/
scb_to_reset->eh_state = SCB_EH_DEV_RESET_REQ;
scb_to_reset->platform_data->targ->flags &=
~ASD_TARG_IN_RECOVERY;
}
asd_hwi_free_scb(asd, scb);
asd_wakeup_sem(&asd->platform_data->ehandler_sem);
break;
}
default:
asd_log(ASD_DBG_ERROR, "Invalid EH State 0x%x.\n",
scb->eh_state);
scb_to_reset->eh_state = SCB_EH_DONE;
scb_to_reset->eh_status = SCB_EH_FAILED;
asd_hwi_free_scb(asd, scb);
asd_wakeup_sem(&asd->platform_data->ehandler_sem);
break;
}
}
static void
asd_hwi_reset_lu_done(struct asd_softc *asd, struct scb *scb,
struct asd_done_list *dl)
{
asd_log(ASD_DBG_ERROR, "DL Opcode = 0x%x.\n", dl->opcode);
/*
* There is a possibility that this post routine is called after
* the SCB timedout. So, only delete the timer if the SCB hasn't
* timedout.
*/
if (scb->eh_state != SCB_EH_TIMEDOUT)
del_timer_sync(&scb->platform_data->timeout);
switch (dl->opcode) {
case TASK_COMP_WO_ERR:
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_SUCCEED;
break;
case TMF_F_W_TC_NOT_FOUND:
case TMF_F_W_TAG_NOT_FOUND:
case TMF_F_W_CONN_HNDL_NOT_FOUND:
case TASK_F_W_NAK_RCVD:
if ((scb->eh_state & SCB_EH_SUSPEND_SENDQ) != 0)
scb->eh_state = SCB_EH_RESUME_SENDQ;
else
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
break;
case SSP_TASK_COMP_W_RESP:
{
union edb *edb;
struct scb *escb;
struct ssp_resp_edb *redb;
struct ssp_resp_iu *riu;
u_int edb_index;
edb = asd_hwi_get_edb_from_dl(asd, scb, dl, &escb, &edb_index);
if (edb == NULL) {
asd_log(ASD_DBG_ERROR, "Invalid EDB recv for SSP "
"comp w/response.\n");
scb->eh_state = SCB_EH_RESUME_SENDQ;
scb->eh_status = SCB_EH_FAILED;
break;
}
redb = &edb->ssp_resp;
riu = &redb->resp_frame.riu;
if (SSP_RIU_DATAPRES(riu) == SSP_RIU_DATAPRES_RESP) {
uint8_t resp_code;
resp_code = ((struct resp_data_iu *)
&riu->data[0])->resp_code;
/* Handle the SSP TMF response code. */
asd_hwi_map_tmf_resp(scb, resp_code);
} else {
/*
* Response Data not available. Protocol error.
* Indicate that LUR failed.
*/
scb->eh_state = SCB_EH_RESUME_SENDQ;
scb->eh_status = SCB_EH_FAILED;
}
asd_hwi_free_edb(asd, escb, edb_index);
break;
}
case TASK_F_W_OPEN_REJECT:
scb->eh_state = SCB_EH_RESUME_SENDQ;
scb->eh_status = SCB_EH_FAILED;
break;
case RESUME_COMPLETE:
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
break;
case TASK_CLEARED:
/*
* Previous error recovery SCB that timed-out and
* was aborted.
* All we need to do here is just free the scb.
*/
asd_hwi_free_scb(asd, scb);
return;
default:
asd_log(ASD_DBG_ERROR, "DL Opcode not handled.\n");
scb->eh_state = SCB_EH_RESUME_SENDQ;
scb->eh_status = SCB_EH_FAILED;
break;
}
asd_hwi_reset_lu(asd, (struct scb *) scb->io_ctx, scb);
}
void
asd_hwi_map_tmf_resp(struct scb *scb, u_int resp_code)
{
/*
* Handle TMF Response upon completion of issuing
* Task Management Function to the target..
* Based on the response code, we will move to certain
* error recovery state.
*/
switch (resp_code) {
case TMF_COMPLETE:
scb->eh_state = SCB_EH_CLR_NXS_REQ;
scb->eh_status = SCB_EH_SUCCEED;
break;
case INVALID_FRAME:
case TMF_FAILED:
case TMF_SUCCEEDED:
case TMF_NOT_SUPPORTED:
case INVALID_LUN:
default:
/* We treat all this as a failure case. */
scb->eh_state = SCB_EH_RESUME_SENDQ;
scb->eh_status = SCB_EH_FAILED;
break;
}
}
/*
* Function:
* asd_hwi_reset_device()
*
* Description:
* Issue a device reset to the failing device.
*/
static void
asd_hwi_reset_device(struct asd_softc *asd, struct scb *scb_to_reset,
struct scb *scb)
{
ASD_LOCK_ASSERT(asd);
asd_log(ASD_DBG_ERROR, "Curr State: 0x%x Status: 0x%x.\n",
scb->eh_state, scb->eh_status);
asd_log(ASD_DBG_ERROR, "scb_to_reset = %p \n",scb_to_reset);
switch (scb->eh_state) {
case SCB_EH_INITIATED:
{
struct asd_target *targ;
struct asd_device *dev;
targ = scb_to_reset->platform_data->targ;
dev = scb_to_reset->platform_data->dev;
if ((targ == NULL) || (dev == NULL)) {
/* This shouldn't happen. */
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
asd_hwi_reset_device(asd, scb_to_reset, scb);
break;
}
/*
* DC: Currently we are not handling error recovery for
* expander.
* Logic for that will be added later on.
*/
if ((targ->device_protocol_type != ASD_DEVICE_PROTOCOL_SCSI) &&
(targ->device_protocol_type != ASD_DEVICE_PROTOCOL_ATA)) {
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
asd_hwi_reset_device(asd, scb_to_reset, scb);
break;
}
scb->platform_data->targ = targ;
scb->platform_data->dev = dev;
/*
* Saving final post routine and the scb_to_reset in
* the first post stack slot. We need to access the
* scb_to_reset during the device reset process.
*/
asd_push_post_stack(asd, scb, (void *) scb_to_reset,
asd_hwi_reset_device_done);
if (SCB_GET_SRC_PORT(scb_to_reset)->management_type ==
ASD_DEVICE_END) {
/* We or'ed it to remember its previous state. */
scb->eh_state = SCB_EH_CLR_NXS_REQ;
} else {
/*
* For device attached behind expander,
* prior to device reset, we will try to
* obtain the error report log of the phy
* that the device is connected to.
*/
scb->eh_state = SCB_EH_PHY_REPORT_REQ;
}
asd_hwi_reset_device(asd, scb_to_reset, scb);
break;
}
case SCB_EH_DEV_RESET_REQ:
{
struct asd_target *targ;
struct asd_port *port;
targ = scb->platform_data->targ;
port = SCB_GET_SRC_PORT(scb);
/*
* Perform a specific device reset for device that is
* direct-attached or expander-attached.
*/
if (port->management_type == ASD_DEVICE_END) {
/* Device is directly attached to the initiator. */
asd_hwi_reset_end_device(asd, scb);
} else {
/* Device is attached behind expander. */
asd_hwi_reset_exp_device(asd, scb);
}
break;
}
case SCB_EH_PHY_NO_OP_REQ:
{
struct asd_phy *phy;
phy = (struct asd_phy *) scb->io_ctx;
/*
* Upon completion of HARD RESET, we need to initialize
* OOB registers to enable hot-plug timer.
* PHY NO OP currently only applied for direct-attached
* device.
*/
asd_hwi_build_control_phy(scb, phy, PHY_NO_OP);
scb->flags |= (SCB_INTERNAL | SCB_ACTIVE | SCB_RECOVERY);
asd_setup_scb_timer(scb, (4 * HZ), asd_scb_eh_timeout);
asd_push_post_stack(asd, scb, scb->io_ctx,
asd_hwi_reset_end_device_done);
asd_hwi_post_scb(asd, scb);
break;
}
case SCB_EH_PHY_REPORT_REQ:
/*
* Obtain the report error log of the phy that the failing
* device is connected to.
* Ideally, we want to traverse the route and obtain the
* error report log of each phy that has pathway to the
* device.
*/
asd_hwi_report_phy_err_log(asd, scb);
break;
case SCB_EH_CLR_NXS_REQ:
/*
* Prior to performing Link Reset or Hard Reset to the
* target, we need to clear the firmware's execution queue
* and suspend the data transimission to the target.
*/
asd_hwi_build_clear_nexus(scb, CLR_NXS_IT_OR_TI,
(SUSPEND_TX | EXEC_Q),
/*ctx*/0);
asd_push_post_stack(asd, scb, (void *) scb_to_reset,
asd_hwi_reset_device_done);
scb->flags |= (SCB_INTERNAL | SCB_ACTIVE | SCB_RECOVERY);
asd_setup_scb_timer(scb, (4 * HZ), asd_scb_eh_timeout);
asd_hwi_post_scb(asd, scb);
break;
case SCB_EH_RESUME_SENDQ:
scb_to_reset->eh_state = SCB_EH_RESUME_SENDQ;
scb_to_reset->eh_status =SCB_EH_SUCCEED;
scb_to_reset->platform_data->targ->flags &=
~ASD_TARG_IN_RECOVERY;
asd_hwi_free_scb(asd, scb);
asd_wakeup_sem(&asd->platform_data->ehandler_sem);
break;
case SCB_EH_DONE:
scb_to_reset->eh_state = scb->eh_state;
scb_to_reset->eh_status = scb->eh_status;
if(!(scb_to_reset->flags & SCB_ABORT_DONE))
{
// scb not retutn from sequencer then set status to fail state
scb_to_reset->eh_status = SCB_EH_FAILED;
}
if ((scb_to_reset->eh_state == SCB_EH_DONE) &&
(scb_to_reset->eh_status == SCB_EH_FAILED)) {
/*
* Failed to perform DEVICE RESET,
* we shall procced with the next level of
* error recovery (Port Reset).
* We need to change the scb eh_state to
* SCB_EH_PORT_RESET_REQ.
*/
scb_to_reset->eh_state = SCB_EH_PORT_RESET_REQ;
scb_to_reset->platform_data->targ->flags &=
~ASD_TARG_IN_RECOVERY;
}
asd_hwi_free_scb(asd, scb);
asd_wakeup_sem(&asd->platform_data->ehandler_sem);
break;
default:
asd_log(ASD_DBG_ERROR, "Invalid EH State 0x%x.\n",
scb->eh_state);
scb_to_reset->eh_state = SCB_EH_DONE;
scb_to_reset->eh_status = SCB_EH_FAILED;
asd_hwi_free_scb(asd, scb);
asd_wakeup_sem(&asd->platform_data->ehandler_sem);
break;
}
}
/*
* Function:
* asd_hwi_reset_device()
*
* Description:
* Issue a device reset to the failing device.
*/
static void
asd_hwi_resume_sendq(struct asd_softc *asd, struct scb *scb_to_reset,
struct scb *scb)
{
ASD_LOCK_ASSERT(asd);
asd_log(ASD_DBG_ERROR, "Curr State: 0x%x Status: 0x%x.\n",
scb->eh_state, scb->eh_status);
asd_log(ASD_DBG_ERROR, "scb_to_reset = %p \n",scb_to_reset);
switch (scb->eh_state) {
case SCB_EH_INITIATED:
{
struct asd_target *targ;
struct asd_device *dev;
targ = scb_to_reset->platform_data->targ;
dev = scb_to_reset->platform_data->dev;
if ((targ == NULL) || (dev == NULL)) {
/* This shouldn't happen. */
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
asd_hwi_resume_sendq(asd, scb_to_reset, scb);
break;
}
/*
* DC: Currently we are not handling error recovery for
* expander.
* Logic for that will be added later on.
*/
if ((targ->device_protocol_type != ASD_DEVICE_PROTOCOL_SCSI) &&
(targ->device_protocol_type != ASD_DEVICE_PROTOCOL_ATA)) {
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
asd_hwi_resume_sendq(asd, scb_to_reset, scb);
break;
}
scb->platform_data->targ = targ;
scb->platform_data->dev = dev;
/*
* Saving final post routine and the scb_to_reset in
* the first post stack slot. We need to access the
* scb_to_reset during the device reset process.
*/
asd_push_post_stack(asd, scb, (void *) scb_to_reset,
asd_hwi_reset_device_done);
scb->eh_state = SCB_EH_RESUME_SENDQ;
asd_hwi_resume_sendq(asd, scb_to_reset, scb);
break;
}
case SCB_EH_RESUME_SENDQ:
{
/*
* Upon completion of Device Reset, we need to issue
* CLEAR NEXUS to the firmware to free up the SCB
* resume data transmission.
* Also, we will be using the first post stack
* we save at the beginning.
*/
asd_hwi_build_clear_nexus(scb, CLR_NXS_IT_OR_TI,
(RESUME_TX|SEND_Q|NOT_IN_Q),
/*ctx*/0);
asd_push_post_stack(asd, scb, (void *) scb_to_reset,
asd_hwi_resume_sendq_done);
scb->flags |= (SCB_INTERNAL | SCB_ACTIVE | SCB_RECOVERY);
asd_setup_scb_timer(scb, (4 * HZ), asd_scb_eh_timeout);
asd_hwi_post_scb(asd, scb);
break;
}
case SCB_EH_DONE:
scb_to_reset->eh_state = scb->eh_state;
scb_to_reset->eh_status = scb->eh_status;
if ((scb_to_reset->eh_state == SCB_EH_DONE) &&
(scb_to_reset->eh_status == SCB_EH_FAILED)) {
/*
* Failed to perform DEVICE RESET,
* we shall procced with the next level of
* error recovery (Port Reset).
* We need to change the scb eh_state to
* SCB_EH_PORT_RESET_REQ.
*/
scb_to_reset->eh_state = SCB_EH_PORT_RESET_REQ;
scb_to_reset->platform_data->targ->flags &=
~ASD_TARG_IN_RECOVERY;
}
asd_hwi_free_scb(asd, scb);
asd_wakeup_sem(&asd->platform_data->ehandler_sem);
break;
default:
asd_log(ASD_DBG_ERROR, "Invalid EH State 0x%x.\n",
scb->eh_state);
scb_to_reset->eh_state = SCB_EH_DONE;
scb_to_reset->eh_status = SCB_EH_FAILED;
asd_hwi_free_scb(asd, scb);
asd_wakeup_sem(&asd->platform_data->ehandler_sem);
break;
}
}
static void
asd_hwi_resume_sendq_done(struct asd_softc *asd, struct scb *scb,
struct asd_done_list *dl)
{
asd_log(ASD_DBG_ERROR, "DL Opcode = 0x%x.\n", dl->opcode);
/*
* There is a possibility that this post routine is called after
* the SCB timedout. So, only delete the timer if the SCB hasn't
* timedout.
*/
if (scb->eh_state != SCB_EH_TIMEDOUT)
del_timer_sync(&scb->platform_data->timeout);
switch (dl->opcode) {
case TASK_COMP_WO_ERR:
{
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_SUCCEED;
break;
}
case TMF_F_W_TC_NOT_FOUND:
case TMF_F_W_TAG_NOT_FOUND:
case TMF_F_W_CONN_HNDL_NOT_FOUND:
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
break;
case TASK_CLEARED:
/*
* Previous error recovery SCB that timed-out and
* was aborted.
* All we need to do here is just free the scb.
*/
asd_log(ASD_DBG_ERROR, "task clear free scb=%p \n", scb);
asd_hwi_free_scb(asd, scb);
return;
default:
asd_log(ASD_DBG_ERROR, "Unhandled DL opcode.\n");
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
break;
}
asd_hwi_resume_sendq(asd, (struct scb *) scb->io_ctx, scb);
}
static void
asd_hwi_reset_device_done(struct asd_softc *asd, struct scb *scb,
struct asd_done_list *dl)
{
asd_log(ASD_DBG_ERROR, "DL Opcode = 0x%x.\n", dl->opcode);
/*
* There is a possibility that this post routine is called after
* the SCB timedout. So, only delete the timer if the SCB hasn't
* timedout.
*/
if (scb->eh_state != SCB_EH_TIMEDOUT)
del_timer_sync(&scb->platform_data->timeout);
switch (dl->opcode) {
case TASK_COMP_WO_ERR:
{
if(scb->eh_state==SCB_EH_CLR_NXS_REQ)
{
struct asd_port *port;
port = SCB_GET_SRC_PORT(scb);
if (port->management_type == ASD_DEVICE_END) {
/*
* For direct-attached SSP target, we need to
* check if it is attached on a wide port.
* If so, we need to issue a HARD RESET on
* one of the phys and LINK RESET on the
* remaining phys.
* For direct-attached SATA/SATAPI target,
* LINK RESET can be done for all the phys
* belong to the port.
* Get which phy(s) that need to be reset.
*/
port->reset_mask = port->conn_mask;
}
scb->eh_state = SCB_EH_DEV_RESET_REQ;
} else {
scb->eh_state = SCB_EH_DONE;
}
scb->eh_status = SCB_EH_SUCCEED;
break;
}
case TMF_F_W_TC_NOT_FOUND:
case TMF_F_W_TAG_NOT_FOUND:
case TMF_F_W_CONN_HNDL_NOT_FOUND:
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
break;
case TASK_CLEARED:
/*
* Previous error recovery SCB that timed-out and
* was aborted.
* All we need to do here is just free the scb.
*/
asd_log(ASD_DBG_ERROR, "task clear free scb=%p \n", scb);
asd_hwi_free_scb(asd, scb);
return;
default:
asd_log(ASD_DBG_ERROR, "Unhandled DL opcode.\n");
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
break;
}
asd_hwi_reset_device(asd, (struct scb *) scb->io_ctx, scb);
}
/*
* Function:
* asd_hwi_reset_end_device()
*
* Description:
* For direct-attached SATA/SATAPI target, device reset is achieved by
* issuing a Link Reset sequence (OOB).
* For direct-attached SSP target, device reset is achieved by issuing
* a Hard Reset.
*/
static void
asd_hwi_reset_end_device(struct asd_softc *asd, struct scb *scb)
{
struct asd_target *targ;
struct asd_port *port;
struct asd_phy *phy;
int found;
targ = scb->platform_data->targ;
port = SCB_GET_SRC_PORT(scb);
found = 0;
/*
* Find the associated phy that need to be reset.
*/
list_for_each_entry(phy, &port->phys_attached, links) {
if ((port->reset_mask & (1 << phy->id)) != 0) {
found = 1;
break;
}
}
if (found != 1) {
/* This shouldn't happen. */
asd_log(ASD_DBG_ERROR,"No PHY to reset, PR Mask: 0x%x "
"PC Mask: 0x%x.\n", port->reset_mask, port->conn_mask);
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
asd_hwi_reset_device(asd,
(struct scb *) scb->post_stack[0].io_ctx,
scb);
return;
}
if (targ->transport_type == ASD_TRANSPORT_SSP) {
/*
* For SSP wide port target, we need to perform a
* HARD RESET only on one of the phys and LINK RESET
* on the remaining phys.
*/
asd_hwi_build_control_phy(scb, phy,
((port->reset_mask == port->conn_mask)
? EXECUTE_HARD_RESET : ENABLE_PHY));
} else {
/*
* For SATA direct-attached end device,
* device port reset is done by re-Enabling the phy
* and hence initiating OOB sequence.
*/
asd_hwi_build_control_phy(scb, phy, ENABLE_PHY);
}
port->reset_mask &= ~(1 << phy->id);
scb->flags |= (SCB_INTERNAL | SCB_ACTIVE | SCB_RECOVERY);
asd_setup_scb_timer(scb, (8 * HZ), asd_scb_eh_timeout);
asd_push_post_stack(asd, scb, (void *) phy,
asd_hwi_reset_end_device_done);
asd_hwi_post_scb(asd, scb);
}
static void
asd_hwi_reset_end_device_done(struct asd_softc *asd, struct scb *scb,
struct asd_done_list *dl)
{
asd_log(ASD_DBG_ERROR, "DL Opcode = 0x%x.\n", dl->opcode);
/*
* There is a possibility that this post routine is called after
* the SCB timedout. So, only delete the timer if the SCB hasn't
* timedout.
*/
if (scb->eh_state != SCB_EH_TIMEDOUT)
del_timer_sync(&scb->platform_data->timeout);
if (scb->eh_status == SCB_EH_SUCCEED) {
if (scb->eh_state != SCB_EH_PHY_NO_OP_REQ) {
/* Check if any remaining phys need to be reset. */
scb->eh_state =
((SCB_GET_SRC_PORT(scb)->reset_mask == 0) ?
SCB_EH_CLR_NXS_REQ : SCB_EH_DEV_RESET_REQ);
}
} else {
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
}
asd_hwi_reset_device(asd, (struct scb *) scb->post_stack[0].io_ctx,
scb);
}
void dumpsmp(uint8_t *smp_req)
{
uint32_t index;
if(smp_req==NULL) return;
asd_print("\nsmp_req: 0x%x", *smp_req );
for( index = 0; index < sizeof(struct SMPRequest); index++)
{
if(!(index % 16))
{
asd_print(" \n");
}
asd_print("%02x ", smp_req[index] );
}
}
static void
asd_hwi_report_phy_err_log(struct asd_softc *asd, struct scb *scb)
{
struct asd_port *port;
struct asd_target *exp_targ;
struct asd_target *targ;
struct Discover *disc;
int phy_id;
targ = scb->platform_data->targ;
/* Expander that the target is attached to. */
exp_targ = targ->parent;
port = SCB_GET_SRC_PORT(scb);
if (exp_targ == NULL) {
/* This shouldn't happen. */
asd_log(ASD_DBG_ERROR, "Parent Expander shouldn't be NULL.\n");
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
asd_hwi_reset_device(asd,
(struct scb *) scb->post_stack[0].io_ctx,
scb);
return;
}
/*
* Find the expander phy id that the target is attached to.
*/
for (phy_id = 0; phy_id < exp_targ->num_phys; phy_id++) {
disc = &(exp_targ->Phy[phy_id].Result);
if (SAS_ISEQUAL(targ->ddb_profile.sas_addr,
disc->AttachedSASAddress))
break;
}
if (phy_id == exp_targ->num_phys) {
/* This shouldn't happen. */
asd_log(ASD_DBG_ERROR, "Corrupted target, inv. phy id.\n");
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
asd_hwi_reset_device(asd,
(struct scb *) scb->post_stack[0].io_ctx,
scb);
return;
}
/* Build a REPORT PHY ERROR LOG SMP request. */
asd_hwi_build_smp_phy_req(port, REPORT_PHY_ERROR_LOG, phy_id, 0);
/* Build a SMP TASK. */
asd_hwi_build_smp_task(scb, exp_targ,
port->dc.SMPRequestBusAddr,
sizeof(struct SMPRequestPhyInput),
port->dc.SMPResponseBusAddr,
sizeof(struct SMPResponseReportPhyErrorLog));
scb->flags |= (SCB_INTERNAL | SCB_ACTIVE | SCB_RECOVERY);
asd_setup_scb_timer(scb, (4 * HZ), asd_scb_eh_timeout);
#ifdef ASD_DEBUG
dumpsmp((uint8_t *)port->dc.SMPRequestFrame);
#endif
asd_push_post_stack(asd, scb, (void *) port,
asd_hwi_reset_exp_device_done);
asd_hwi_post_scb(asd, scb);
}
/*
* Function:
* asd_hwi_reset_exp_device()
*
* Description:
* For device that is attached behind an expander device, device reset
* is achieved by issuing SMP PHY CONTROL with a phy operation of:
* - HARD RESET for SSP and STP device port.
* - LINK RESET for SATA/SATAPI device port.
*/
static void
asd_hwi_reset_exp_device(struct asd_softc *asd, struct scb *scb)
{
struct asd_target *exp_targ;
struct asd_target *targ;
struct asd_port *port;
struct Discover *disc;
int phy_id;
port = SCB_GET_SRC_PORT(scb);
targ = scb->platform_data->targ;
/* Expander that the target is attached to. */
exp_targ = targ->parent;
if (exp_targ == NULL) {
/* This shouldn't happen. */
asd_log(ASD_DBG_ERROR, "Parent Expander shouldn't be NULL.\n");
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
asd_hwi_reset_device(asd,
(struct scb *) scb->post_stack[0].io_ctx,
scb);
return;
}
/*
* Find the expander phy id that the target is attached to.
*/
for (phy_id = 0; phy_id < exp_targ->num_phys; phy_id++) {
disc = &(exp_targ->Phy[phy_id].Result);
if (SAS_ISEQUAL(targ->ddb_profile.sas_addr,
disc->AttachedSASAddress))
break;
}
if (phy_id == exp_targ->num_phys) {
/* This shouldn't happen. */
asd_log(ASD_DBG_ERROR, "Corrupted target, inv. phy id.\n");
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
asd_hwi_reset_device(asd,
(struct scb *) scb->post_stack[0].io_ctx,
scb);
return;
}
/*
* For SSP/STP target port, CONTROL PHY-HARD RESET will be issued.
* For SATA/SATAPI target port, CONTROL PHY-LINK RESET will be issued.
*/
asd_hwi_build_smp_phy_req(
port, PHY_CONTROL, phy_id,
((targ->transport_type == ASD_TRANSPORT_ATA
|| targ->transport_type ==ASD_TRANSPORT_STP) ? LINK_RESET :
HARD_RESET));
/* Build a SMP REQUEST. */
asd_hwi_build_smp_task(scb, exp_targ,
port->dc.SMPRequestBusAddr,
sizeof(struct SMPRequestPhyControl),
port->dc.SMPResponseBusAddr,
sizeof(struct SMPResponsePhyControl));
scb->flags |= (SCB_INTERNAL | SCB_ACTIVE | SCB_RECOVERY);
asd_setup_scb_timer(scb, (8 * HZ), asd_scb_eh_timeout);
#ifdef ASD_DEBUG
dumpsmp((uint8_t *)port->dc.SMPRequestFrame);
#endif
asd_push_post_stack(asd, scb, (void *) port,
asd_hwi_reset_exp_device_done);
asd_hwi_post_scb(asd, scb);
}
static void
asd_hwi_reset_exp_device_done(struct asd_softc *asd, struct scb *scb,
struct asd_done_list *dl)
{
asd_log(ASD_DBG_ERROR, "DL Opcode = 0x%x.\n", dl->opcode);
/*
* There is a possibility that this post routine is called after
* the SCB timedout. So, only delete the timer if the SCB hasn't
* timedout.
*/
if (scb->eh_state != SCB_EH_TIMEDOUT)
del_timer_sync(&scb->platform_data->timeout);
switch (dl->opcode) {
case TASK_COMP_WO_ERR:
{
struct asd_port *port;
port = (struct asd_port *) scb->io_ctx;
/* Check the SMP Response function result. */
if (port->dc.SMPResponseFrame->FunctionResult ==
SMP_FUNCTION_ACCEPTED) {
if (scb->eh_state == SCB_EH_PHY_REPORT_REQ) {
asd_hwi_dump_phy_err_log(port, scb);
// do the first time clear nexus after PHY report error
scb->eh_state = SCB_EH_CLR_NXS_REQ;
} else {
scb->eh_state = SCB_EH_RESUME_SENDQ;
}
scb->eh_status = SCB_EH_SUCCEED;
} else {
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
}
break;
}
case TASK_CLEARED:
/*
* Previous error recovery SCB that timed-out and
* was aborted.
* All we need to do here is just free the scb.
*/
asd_hwi_free_scb(asd, scb);
return;
case TASK_F_W_SMPRSP_TO:
case TASK_F_W_SMP_XMTRCV_ERR:
default:
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
break;
}
asd_hwi_reset_device(asd, (struct scb *) scb->post_stack[0].io_ctx,
scb);
}
static void
asd_hwi_dump_phy_err_log(struct asd_port *port, struct scb *scb)
{
struct SMPResponseReportPhyErrorLog *report_phy_log;
struct asd_target *targ;
struct asd_device *dev;
report_phy_log = (struct SMPResponseReportPhyErrorLog *)
&(port->dc.SMPResponseFrame->Response);
targ = scb->platform_data->targ;
dev = scb->platform_data->dev;
asd_print("REPORT PHY ERROR LOG\n");
asd_print("---------------------\n");
asd_print("Phy #%d of Expander 0x%llx.\n",
report_phy_log->PhyIdentifier, asd_be64toh(
*((uint64_t *) targ->parent->ddb_profile.sas_addr)));
asd_print("Attached device:\n");
asd_print("Scsi %d Ch %d Tgt %d Lun %d, SAS Addr: 0x%llx.\n",
targ->softc->platform_data->scsi_host->host_no,
dev->ch, dev->id, dev->lun, asd_be64toh(
*((uint64_t *) targ->ddb_profile.sas_addr)));
asd_print("\nPHY ERROR COUNTS\n");
asd_print("----------------\n");
asd_print("Invalid Dword Count: %d.\n",
report_phy_log->InvalidDuint16_tCount);
asd_print("Disparity Error Count: %d.\n",
report_phy_log->DisparityErrorCount);
asd_print("Loss of Dword Synchronization Count: %d.\n",
report_phy_log->LossOfDuint16_tSynchronizationCount);
asd_print("Phy Reset Problem Count: %d.\n",
report_phy_log->PhyResetProblemCount);
}
/*
* Function:
* asd_hwi_reset_port()
*
* Description:
* Issue a HARD/LINK RESET to the failing port.
*/
static void
asd_hwi_reset_port(struct asd_softc *asd, struct scb *scb_to_reset,
struct scb *scb)
{
ASD_LOCK_ASSERT(asd);
asd_log(ASD_DBG_ERROR, "Curr State: 0x%x Status: 0x%x.\n",
scb->eh_state, scb->eh_status);
asd_log(ASD_DBG_ERROR, "reset port scb=%p scb_to_reset = %p\n",scb,scb_to_reset);
switch (scb->eh_state) {
case SCB_EH_INITIATED:
{
struct asd_port *port;
struct asd_target *targ;
port = SCB_GET_SRC_PORT(scb_to_reset);
if (port == NULL) {
asd_log(ASD_DBG_ERROR," Invalid port to reset.\n");
scb->eh_state = SCB_EH_DONE;
scb->eh_state = SCB_EH_FAILED;
asd_hwi_reset_port(asd, scb_to_reset, scb);
break;
}
/*
* Freeze all the targets' queue attached to the port that
* we are about to reset.
*/
list_for_each_entry(targ, &port->targets, all_domain_targets) {
targ->qfrozen++;
}
/*
* Saving final post routine and the scb_to_reset in
* the first post stack slot. We need to access the
* scb_to_reset during the device reset process.
*/
asd_push_post_stack(asd, scb, (void *) scb_to_reset,
asd_hwi_reset_port_done);
/* Bitmask of the phys to perform reset. */
port->reset_mask = port->conn_mask;
scb->platform_data->targ = scb_to_reset->platform_data->targ;
scb->platform_data->dev = scb_to_reset->platform_data->dev;
scb->eh_state = SCB_EH_CLR_NXS_REQ;
asd_hwi_reset_port(asd, scb_to_reset, scb);
break;
}
case SCB_EH_CLR_NXS_REQ:
asd_hwi_build_clear_nexus(scb, CLR_NXS_I_OR_T,
/*parm*/0, /*ctx*/0);
asd_push_post_stack(asd, scb, (void *) scb_to_reset,
asd_hwi_reset_port_done);
scb->flags |= (SCB_INTERNAL | SCB_ACTIVE | SCB_RECOVERY);
asd_setup_scb_timer(scb, (4 * HZ), asd_scb_eh_timeout);
asd_hwi_post_scb(asd, scb);
break;
case SCB_EH_PORT_RESET_REQ:
{
struct asd_port *port;
struct asd_phy *phy;
int found;
found = 0;
port = SCB_GET_SRC_PORT(scb_to_reset);
list_for_each_entry(phy, &port->phys_attached, links) {
if ((port->reset_mask & (1 << phy->id)) != 0) {
found = 1;
break;
}
}
if (found != 1) {
/* This shouldn't happen. */
asd_log(ASD_DBG_ERROR,"No PHY to reset, PR Mask: 0x%x "
"PC Mask: 0x%x.\n",
port->reset_mask, port->conn_mask);
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
asd_hwi_reset_port(asd, scb_to_reset, scb);
break;
}
/*
* For SSP initiator wide port, we need to perform a
* HARD RESET only on one of the phys and LINK RESET on
* the remaining phys.
*/
asd_hwi_build_control_phy(scb, phy,
((port->reset_mask == port->conn_mask)
? EXECUTE_HARD_RESET : ENABLE_PHY));
port->reset_mask &= ~(1 << phy->id);
scb->flags |= (SCB_INTERNAL | SCB_ACTIVE | SCB_RECOVERY);
asd_setup_scb_timer(scb, (8 * HZ), asd_scb_eh_timeout);
asd_push_post_stack(asd, scb, (void *) phy,
asd_hwi_reset_port_done);
asd_hwi_post_scb(asd, scb);
break;
}
case SCB_EH_PHY_NO_OP_REQ:
{
struct asd_phy *phy;
phy = (struct asd_phy *) scb->io_ctx;
/*
* Upon completion of HARD RESET, we need to initialize
* OOB registers to enable hot-plug timer.
*/
asd_hwi_build_control_phy(scb, phy, PHY_NO_OP);
scb->flags |= (SCB_INTERNAL | SCB_ACTIVE | SCB_RECOVERY);
asd_setup_scb_timer(scb, (4 * HZ), asd_scb_eh_timeout);
asd_push_post_stack(asd, scb, scb->io_ctx,
asd_hwi_reset_port_done);
asd_hwi_post_scb(asd, scb);
break;
}
case SCB_EH_DONE:
{
struct asd_port *port;
struct asd_target *targ;
port = SCB_GET_SRC_PORT(scb_to_reset);
/* Unfreeze all the targets. */
list_for_each_entry(targ, &port->targets, all_domain_targets) {
targ->qfrozen--;
asd_log(ASD_DBG_INFO,"clear freezen ptr=%p num=%d\n",targ,targ->qfrozen);
}
scb_to_reset->eh_state = scb->eh_state;
scb_to_reset->eh_status = scb->eh_status;
asd_hwi_free_scb(asd, scb);
asd_wakeup_sem(&asd->platform_data->ehandler_sem);
break;
}
default:
asd_log(ASD_DBG_ERROR, "Invalid State.\n");
scb_to_reset->eh_state = SCB_EH_DONE;
scb_to_reset->eh_status = SCB_EH_FAILED;
asd_hwi_free_scb(asd, scb);
asd_wakeup_sem(&asd->platform_data->ehandler_sem);
break;
}
}
static void
asd_hwi_reset_port_done(struct asd_softc *asd, struct scb *scb,
struct asd_done_list *dl)
{
asd_log(ASD_DBG_ERROR, "DL Opcode = 0x%x.\n", dl->opcode);
/*
* There is a possibility that this post routine is called after
* the SCB timedout. So, only delete the timer if the SCB hasn't
* timedout.
*/
if (scb->eh_state != SCB_EH_TIMEDOUT)
del_timer_sync(&scb->platform_data->timeout);
/* CLR NXS completion. */
if (dl->opcode == TASK_COMP_WO_ERR) {
scb->eh_state = SCB_EH_PORT_RESET_REQ;
} else if (scb->eh_status == SCB_EH_SUCCEED) {
if (scb->eh_state != SCB_EH_PHY_NO_OP_REQ) {
/* Check if any remaining phys need to be reset. */
scb->eh_state =
((SCB_GET_SRC_PORT(scb)->reset_mask == 0) ?
SCB_EH_DONE : SCB_EH_PORT_RESET_REQ);
}
} else {
scb->eh_state = SCB_EH_DONE;
scb->eh_status = SCB_EH_FAILED;
}
asd_hwi_reset_port(asd,
(struct scb *) scb->post_stack[0].io_ctx,
scb);
}
/*************************** NVRAM access utilities ***************************/
#if NVRAM_SUPPORT
/*
* Function:
* asd_hwi_poll_nvram()
*
* Description:
* This routine will poll for the NVRAM to be ready to accept new
* command.
*/
static int
asd_hwi_poll_nvram(struct asd_softc *asd)
{
uint8_t nv_data;
uint8_t toggle_data;
int loop_cnt;
loop_cnt = 5000;
while (loop_cnt) {
nv_data = asd_hwi_swb_read_byte(asd,
asd->hw_profile.nv_flash_bar);
toggle_data = (nv_data ^ asd_hwi_swb_read_byte(asd,
asd->hw_profile.nv_flash_bar));
if (toggle_data == 0) {
return (0);
} else {
if (((toggle_data == 0x04) && ((loop_cnt - 1) == 0)) ||
((toggle_data & 0x40) && (toggle_data & 0x20))) {
return (-1);
}
}
loop_cnt--;
asd_delay(ASD_DELAY_COUNT);
}
return (-1);
}
static int
asd_hwi_chk_write_status(struct asd_softc *asd, uint32_t sector_addr,
uint8_t erase_flag)
{
uint32_t read_addr;
uint32_t loop_cnt;
uint8_t nv_data1, nv_data2;
uint8_t toggle_bit1/*, toggle_bit2*/;
/*
* Read from DQ2 requires sector address
* while it's dont care for DQ6
*/
/* read_addr = asd->hw_profile.nv_flash_bar + sector_addr;*/
read_addr = asd->hw_profile.nv_flash_bar;
loop_cnt = 50000;
while (loop_cnt) {
nv_data1 = asd_hwi_swb_read_byte(asd, read_addr);
nv_data2 = asd_hwi_swb_read_byte(asd, read_addr);
toggle_bit1 = ((nv_data1 & FLASH_STATUS_BIT_MASK_DQ6)
^ (nv_data2 & FLASH_STATUS_BIT_MASK_DQ6));
/* toggle_bit2 = ((nv_data1 & FLASH_STATUS_BIT_MASK_DQ2)
^ (nv_data2 & FLASH_STATUS_BIT_MASK_DQ2));*/
if (toggle_bit1 == 0) {
return (0);
} else {
if (nv_data2 & FLASH_STATUS_BIT_MASK_DQ5) {
nv_data1 = asd_hwi_swb_read_byte(asd,
read_addr);
nv_data2 = asd_hwi_swb_read_byte(asd,
read_addr);
toggle_bit1 =
((nv_data1 & FLASH_STATUS_BIT_MASK_DQ6)
^ (nv_data2 & FLASH_STATUS_BIT_MASK_DQ6));
/*
toggle_bit2 =
((nv_data1 & FLASH_STATUS_BIT_MASK_DQ2)
^ (nv_data2 & FLASH_STATUS_BIT_MASK_DQ2));
*/
if (toggle_bit1 == 0) {
return 0;
}
}
}
loop_cnt--;
/*
* ERASE is a sector-by-sector operation and requires
* more time to finish while WRITE is byte-byte-byte
* operation and takes lesser time to finish.
*
* For some strange reason a reduced ERASE delay gives different
* behaviour across different spirit boards. Hence we set
* a optimum balance of 50mus for ERASE which works well
* across all boards.
*/
if (erase_flag) {
asd_delay(FLASH_STATUS_ERASE_DELAY_COUNT);
} else {
asd_delay(FLASH_STATUS_WRITE_DELAY_COUNT);
}
}
return (-1);
}
/*
* Function:
* asd_hwi_reset_nvram()
*
* Description:
* Reset the NVRAM section.
*/
static int
asd_hwi_reset_nvram(struct asd_softc *asd)
{
/* Poll till NVRAM is ready for new command. */
if (asd_hwi_poll_nvram(asd) != 0)
return (-1);
asd_hwi_swb_write_byte(asd, asd->hw_profile.nv_flash_bar, NVRAM_RESET);
/* Poll if the command is successfully written. */
if (asd_hwi_poll_nvram(asd) != 0)
return (-1);
return (0);
}
/*
* Function:
* asd_hwi_search_nv_cookie()
*
* Description:
* Search the cookie in NVRAM.
* If found, return the address offset of the cookie.
*/
int
asd_hwi_search_nv_cookie(struct asd_softc *asd, uint32_t *addr,
struct asd_flash_dir_layout *pflash_dir_buf)
{
struct asd_flash_dir_layout flash_dir;
uint8_t cookie_to_find[32]="*** ADAPTEC FLASH DIRECTORY *** ";
void *dest_buf;
uint32_t nv_addr;
int cookie_found;
u_int bytes_read;
memset(&flash_dir, 0x0, sizeof(flash_dir));
dest_buf = &flash_dir;
cookie_found = 0;
nv_addr = 0;
while (nv_addr < NVRAM_MAX_BASE_ADR) {
if (asd_hwi_read_nv_segment(asd, NVRAM_NO_SEGMENT_ID,
dest_buf, nv_addr,
sizeof(flash_dir),
&bytes_read)
!= 0)
return (-1);
if (memcmp(flash_dir.cookie,
&cookie_to_find[0],
NVRAM_COOKIE_SIZE) == 0) {
cookie_found = 1;
if (pflash_dir_buf != NULL) {
memcpy(pflash_dir_buf, &flash_dir,
sizeof(flash_dir));
}
break;
}
nv_addr += NVRAM_NEXT_ENTRY_OFFSET;
}
if (cookie_found == 0) {
return (-1);
}
*addr = nv_addr;
asd->hw_profile.nv_cookie_addr = nv_addr;
asd->hw_profile.nv_cookie_found = 1;
return (0);
}
/*
* Function:
* asd_hwi_search_nv_segment()
*
* Description:
* Search the requested NVRAM segment.
* If exists, the segment offset, attributes, pad_size and image_size
* will be returned.
*/
int
asd_hwi_search_nv_segment(struct asd_softc *asd, u_int segment_id,
uint32_t *offset, uint32_t *pad_size,
uint32_t *image_size, uint32_t *attr)
{
struct asd_flash_dir_layout flash_dir;
struct asd_fd_entry_layout fd_entry;
uint32_t nv_addr;
int segment_found;
u_int bytes_read;
u_int i;
/*
* Check if we have NVRAM base addr for the FLASH directory layout.
*/
if (asd->hw_profile.nv_cookie_found != 1) {
if (asd_hwi_search_nv_cookie(asd, &nv_addr,
&flash_dir) != 0) {
asd_log(ASD_DBG_ERROR, "Failed to search NVRAM "
"cookie.\n");
return (-1);
}
} else {
nv_addr = asd->hw_profile.nv_cookie_addr;
}
nv_addr += NVRAM_FIRST_DIR_ENTRY;
memset(&fd_entry, 0x0, sizeof(struct asd_fd_entry_layout));
segment_found = 0;
for (i = 0; i < NVRAM_MAX_ENTRIES; i++) {
if (asd_hwi_read_nv_segment(asd, NVRAM_NO_SEGMENT_ID,
&fd_entry, nv_addr,
sizeof(struct asd_fd_entry_layout),
&bytes_read) != 0) {
return (-1);
}
if ((fd_entry.attr & FD_ENTRYTYPE_CODE) == segment_id) {
segment_found = 1;
break;
}
nv_addr += sizeof(struct asd_fd_entry_layout);
}
if (segment_found == 0) {
return (-1);
}
*offset = fd_entry.offset;
*pad_size = fd_entry.pad_size;
*attr = ((fd_entry.attr & FD_SEGMENT_ATTR) ? 1 : 0);
if ((segment_id != NVRAM_CTRL_A_SETTING) &&
(segment_id != NVRAM_MANUF_TYPE)) {
*image_size = fd_entry.image_size;
} else {
*image_size = NVRAM_INVALID_SIZE;
}
return (0);
}
/*
* Function:
* asd_hwi_read_nv_segment()
*
* Description:
* Retrieves data from an NVRAM segment.
*/
int
asd_hwi_read_nv_segment(struct asd_softc *asd, uint32_t segment_id, void *dest,
uint32_t src_offset, uint32_t bytes_to_read,
uint32_t *bytes_read)
{
uint8_t *dest_buf;
uint32_t nv_offset;
uint32_t pad_size, image_size, attr;
uint32_t i;
/* Reset the NVRAM. */
if (asd_hwi_reset_nvram(asd) != 0)
return (-1);
nv_offset = 0;
if (segment_id != NVRAM_NO_SEGMENT_ID) {
if (asd_hwi_search_nv_segment(asd, segment_id, &nv_offset,
&pad_size, &image_size,
&attr) != 0) {
return (-1);
}
}
nv_offset = asd->hw_profile.nv_flash_bar + nv_offset + src_offset;
dest_buf = (uint8_t *) dest;
*bytes_read = 0;
if (asd_hwi_reset_nvram(asd) != 0)
return (-1);
for (i = 0; i < bytes_to_read; i++) {
*(dest_buf + i) = asd_hwi_swb_read_byte(asd, (nv_offset + i));
if (asd_hwi_poll_nvram(asd) != 0) {
return (-1);
}
}
*bytes_read = i;
return (0);
}
/*
* Function:
* asd_hwi_write_nv_segment()
*
* Description:
* Writes data to an NVRAM segment.
*/
int
asd_hwi_write_nv_segment(struct asd_softc *asd, void *src, uint32_t segment_id,
uint32_t dest_offset, uint32_t bytes_to_write)
{
uint8_t *src_buf;
uint32_t nv_offset, nv_flash_bar, i;
uint32_t pad_size, image_size, attr;
nv_flash_bar = asd->hw_profile.nv_flash_bar;
src_buf = NULL;
nv_offset = 0;
attr = 0;
pad_size = 0;
image_size = 0;
if (asd_hwi_reset_nvram(asd) != 0) {
return (-1);
}
if (segment_id != NVRAM_NO_SEGMENT_ID) {
if (asd_hwi_search_nv_segment(asd, segment_id, &nv_offset,
&pad_size, &image_size, &attr) != 0) {
return (-1);
}
if ((bytes_to_write > pad_size) || (dest_offset != 0)) {
return (-1);
}
}
nv_offset += dest_offset;
if (segment_id == NVRAM_NO_SEGMENT_ID
|| attr == NVRAM_SEGMENT_ATTR_ERASEWRITE) {
if (asd_hwi_erase_nv_sector(asd, nv_offset) != 0) {
printk("<1>adp94xx: Erase failed at offset:0x%x\n",
nv_offset);
return (-1);
}
}
if (asd_hwi_reset_nvram(asd) != 0) {
return (-1);
}
src_buf = (uint8_t *)src;
for (i = 0; i < bytes_to_write; i++) {
/* Setup program command sequence */
switch (asd->hw_profile.flash_method) {
case FLASH_METHOD_A:
{
asd_hwi_swb_write_byte(asd,
(nv_flash_bar + 0xAAA), 0xAA);
asd_hwi_swb_write_byte(asd,
(nv_flash_bar + 0x555), 0x55);
asd_hwi_swb_write_byte(asd,
(nv_flash_bar + 0xAAA), 0xA0);
asd_hwi_swb_write_byte(asd,
(nv_flash_bar + nv_offset + i),
(*(src_buf + i)));
break;
}
case FLASH_METHOD_B:
{
asd_hwi_swb_write_byte(asd,
(nv_flash_bar + 0x555), 0xAA);
asd_hwi_swb_write_byte(asd,
(nv_flash_bar + 0x2AA), 0x55);
asd_hwi_swb_write_byte(asd,
(nv_flash_bar + 0x555), 0xA0);
asd_hwi_swb_write_byte(asd,
(nv_flash_bar + nv_offset + i),
(*(src_buf + i)));
break;
}
default:
break;
}
if (asd_hwi_chk_write_status(asd, (nv_offset + i),
0 /* WRITE operation */) != 0) {
printk("<1>adp94xx: Write failed at offset:0x%x\n",
nv_flash_bar + nv_offset + i);
return -1;
}
}
if (asd_hwi_reset_nvram(asd) != 0) {
return (-1);
}
return (0);
}
/*
* Function:
* asd_hwi_erase_nv_sector()
*
* Description:
* Erase the requested NVRAM sector.
*/
static int
asd_hwi_erase_nv_sector(struct asd_softc *asd, uint32_t sector_addr)
{
uint32_t nv_flash_bar;
nv_flash_bar = asd->hw_profile.nv_flash_bar;
if (asd_hwi_poll_nvram(asd) != 0) {
return (-1);
}
/*
* Erasing an NVRAM sector needs to be done in six consecutive
* write cyles.
*/
switch (asd->hw_profile.flash_method) {
case FLASH_METHOD_A:
asd_hwi_swb_write_byte(asd, (nv_flash_bar + 0xAAA), 0xAA);
asd_hwi_swb_write_byte(asd, (nv_flash_bar + 0x555), 0x55);
asd_hwi_swb_write_byte(asd, (nv_flash_bar + 0xAAA), 0x80);
asd_hwi_swb_write_byte(asd, (nv_flash_bar + 0xAAA), 0xAA);
asd_hwi_swb_write_byte(asd, (nv_flash_bar + 0x555), 0x55);
asd_hwi_swb_write_byte(asd, (nv_flash_bar + sector_addr), 0x30);
break;
case FLASH_METHOD_B:
asd_hwi_swb_write_byte(asd, (nv_flash_bar + 0x555), 0xAA);
asd_hwi_swb_write_byte(asd, (nv_flash_bar + 0x2AA), 0x55);
asd_hwi_swb_write_byte(asd, (nv_flash_bar + 0x555), 0x80);
asd_hwi_swb_write_byte(asd, (nv_flash_bar + 0x555), 0xAA);
asd_hwi_swb_write_byte(asd, (nv_flash_bar + 0x2AA), 0x55);
asd_hwi_swb_write_byte(asd, (nv_flash_bar + sector_addr), 0x30);
break;
default:
break;
}
if (asd_hwi_chk_write_status(asd, sector_addr,
1 /* ERASE operation */) != 0) {
return (-1);
}
return (0);
}
/*
* Function:
* asd_hwi_verify_nv_checksum()
*
* Description:
* Verify if the checksum for particular NV segment is correct.
*/
static int
asd_hwi_verify_nv_checksum(struct asd_softc *asd, u_int segment_id,
uint8_t *segment_ptr, u_int bytes_to_read)
{
uint32_t offset;
u_int pad_size;
u_int image_size;
u_int attr;
u_int bytes_read;
int checksum_bytes;
uint16_t sum;
uint16_t *seg_ptr;
u_short i;
if (asd_hwi_search_nv_segment(asd, segment_id, &offset, &pad_size,
&image_size, &attr) != 0) {
asd_log(ASD_DBG_ERROR, "Requested segment not found in "
"the NVRAM.\n");
return (-1);
}
memset(segment_ptr, 0x0, bytes_to_read);
if (asd_hwi_read_nv_segment(asd, NVRAM_NO_SEGMENT_ID, segment_ptr,
offset, bytes_to_read, &bytes_read) != 0) {
asd_log(ASD_DBG_ERROR, "Failed to read NVRAM segment %d.\n",
NVRAM_NO_SEGMENT_ID);
return (-1);
}
if (asd_hwi_reset_nvram(asd) != 0) {
asd_log(ASD_DBG_ERROR, "Failed to reset NVRAM.\n");
return (-1);
}
seg_ptr = (uint16_t *) segment_ptr;
/*
* checksum_bytes is equivalent to the size of the layout.
* The size of layout is available at the offset of 8.
*/
checksum_bytes = (*(seg_ptr + 4) / 2);
offset += asd->hw_profile.nv_flash_bar;
sum = 0;
for (i = 0; i < checksum_bytes; i++)
sum += asd_hwi_swb_read_word(asd, (offset + (i*2)));
if (sum != 0) {
asd_log(ASD_DBG_ERROR, "Checksum verification failed.\n");
return (-1);
}
return (0);
}
/*
* Function:
* asd_hwi_get_nv_config()
*
* Description:
* Retrieves NVRAM configuration for the controller.
*/
static int
asd_hwi_get_nv_config(struct asd_softc *asd)
{
struct asd_manuf_base_seg_layout manuf_layout;
struct asd_pci_layout pci_layout;
uint32_t offset;
u_int bytes_read;
if (asd_hwi_check_flash(asd) < 0)
return -1;
asd->hw_profile.nv_exist = 0;
/* Verify if the controller NVRAM has CTRL_A_SETTING type. */
if (asd_hwi_verify_nv_checksum(asd, NVRAM_CTRL_A_SETTING,
(uint8_t *) &pci_layout,
sizeof(struct asd_pci_layout)) != 0) {
/*
* CTRL_A type verification failed, verify if the controller
* has NVRAM CTRL_A_DEFAULT type.
*/
if (asd_hwi_verify_nv_checksum(asd, NVRAM_CTRL_A_DEFAULT,
(uint8_t *) &pci_layout,
sizeof(struct asd_pci_layout))
!= 0)
return (-1);
asd->hw_profile.nv_segment_type = NVRAM_CTRL_A_DEFAULT;
} else {
asd->hw_profile.nv_segment_type = NVRAM_CTRL_A_SETTING;
asd->hw_profile.nv_exist = 1;
}
offset = 0;
memset(&manuf_layout, 0x0, sizeof (struct asd_manuf_base_seg_layout));
/* Retrieves Controller Manufacturing NVRAM setting. */
if (asd_hwi_read_nv_segment(asd, NVRAM_MANUF_TYPE, &manuf_layout,
offset, sizeof(struct asd_manuf_base_seg_layout),
&bytes_read) != 0) {
return (-1);
}
memcpy(asd->hw_profile.wwn, manuf_layout.base_sas_addr,
ASD_MAX_WWN_LEN);
return (0);
}
/*
* Function:
* asd_hwi_search_nv_id()
*
* Description:
* Search for the requested NV setting ID. If successful copy contents
* to the destination buffer and set appropriate value in offset.
*/
static int
asd_hwi_search_nv_id(struct asd_softc *asd, u_int setting_id, void *dest,
u_int *src_offset, u_int bytes_to_read)
{
struct asd_settings_layout *psettings;
uint32_t offset;
uint32_t bytes_read;
offset = 0;
bytes_read = 0;
psettings = (struct asd_settings_layout *)dest;
while (1) {
if (asd_hwi_read_nv_segment(asd,
asd->hw_profile.nv_segment_type,
psettings,
offset,
bytes_to_read,
&bytes_read) != 0) {
return (-1);
}
if (psettings->id == setting_id) {
break;
} else {
if (psettings->next_ptr == 0)
return -1;
offset = (uint32_t)offset + psettings->next_ptr;
}
}
*src_offset = offset;
return (0);
}
static int
asd_hwi_get_nv_phy_settings(struct asd_softc *asd)
{
struct asd_phy_settings_layout phy_settings;
struct asd_phy_settings_entry_layout *phy_entry;
uint32_t offset;
uint32_t bytes_to_read;
struct asd_phy *phy;
u_int bytes_read;
u_int phy_id;
u_char settings_found;
if (asd->hw_profile.nv_exist != 1)
return -1;
/*
* NVRAM setting exists, retrieve Phys user settings, such
* as SAS address, connection rate, and attributes.
*/
offset = 0;
settings_found = 0;
if (asd_hwi_search_nv_id(asd, NVRAM_PHY_SETTINGS_ID,
&phy_settings, &offset, sizeof(phy_settings))) {
return -1;
}
bytes_to_read = phy_settings.num_phys * sizeof(*phy_entry);
if ((phy_entry = asd_alloc_mem(bytes_to_read, GFP_ATOMIC))
== NULL) {
return (-1);
}
if (asd_hwi_read_nv_segment(asd,
asd->hw_profile.nv_segment_type,
phy_entry,
offset + sizeof(phy_settings),
bytes_to_read,
&bytes_read) != 0) {
asd_free_mem(phy_entry);
return (-1);
} else {
settings_found = 1;
}
if (settings_found == 1) {
asd->hw_profile.max_phys = phy_settings.num_phys;
for (phy_id = 0;
phy_id < asd->hw_profile.max_phys;
phy_id++) {
if ((phy = asd->phy_list[phy_id]) == NULL)
continue;
memcpy(phy->sas_addr,
phy_entry[phy_id].sas_addr,
SAS_ADDR_LEN);
/*
* if an invalid link rate is specified,
* the existing default value is used.
*/
asd_hwi_map_lrate_from_sas(
(phy_entry[phy_id].link_rate
& PHY_MIN_LINK_RATE_MASK),
&phy->min_link_rate);
asd_hwi_map_lrate_from_sas(
((phy_entry[phy_id].link_rate
& PHY_MAX_LINK_RATE_MASK) >> 4),
&phy->max_link_rate);
/* TBD: crc */
}
}
asd_free_mem(phy_entry);
return 0;
}
static void
asd_hwi_get_nv_phy_params(struct asd_softc *asd)
{
struct asd_manuf_base_seg_layout manuf_layout;
struct asd_manuf_phy_param_layout phy_param;
struct asd_phy_desc_format *pphy_desc;
struct asd_phy *phy;
uint32_t offset;
uint32_t bytes_to_read;
uint32_t bytes_read;
u_int phy_id;
/* Set the phy parms to the default value. */
for (phy_id = 0; phy_id < asd->hw_profile.max_phys; phy_id++) {
if ((phy = asd->phy_list[phy_id]) == NULL)
continue;
phy->phy_state = PHY_STATE_DEFAULT;
phy->phy_ctl0 = PHY_CTL0_DEFAULT;
phy->phy_ctl1 = PHY_CTL1_DEFAULT;
phy->phy_ctl2 = PHY_CTL2_DEFAULT;
phy->phy_ctl3 = PHY_CTL3_DEFAULT;
}
if (asd_hwi_verify_nv_checksum(asd, NVRAM_MANUF_TYPE,
(uint8_t *) &manuf_layout,
sizeof(struct asd_manuf_base_seg_layout))
!= 0) {
asd_log(ASD_DBG_ERROR, "Failed verifying checksum for "
"NVRAM MANUFACTURING LAYOUT.\n");
goto exit;
}
offset = 0;
memset(&phy_param, 0x0, sizeof(phy_param));
if (asd_hwi_get_nv_manuf_seg(asd, &phy_param,
sizeof(phy_param), &offset,
NVRAM_MNF_PHY_PARAM_SIGN) != 0)
goto exit;
if (phy_param.num_phy_desc > asd->hw_profile.max_phys)
phy_param.num_phy_desc = asd->hw_profile.max_phys;
bytes_to_read = phy_param.num_phy_desc * phy_param.phy_desc_size;
if ((pphy_desc = asd_alloc_mem(bytes_to_read, GFP_ATOMIC)) == NULL)
goto exit;
offset += sizeof(phy_param);
if (asd_hwi_read_nv_segment(asd, NVRAM_MANUF_TYPE, pphy_desc, offset,
bytes_to_read, &bytes_read) != 0) {
asd_free_mem(pphy_desc);
goto exit;
}
for (phy_id = 0; phy_id < asd->hw_profile.max_phys; phy_id++) {
if ((phy = asd->phy_list[phy_id]) == NULL)
continue;
phy->phy_state = (pphy_desc[phy_id].state & PHY_STATE_MASK);
phy->phy_ctl0 &= ~PHY_CTL0_MASK;
phy->phy_ctl0 |= (pphy_desc[phy_id].ctl0 & PHY_CTL0_MASK);
phy->phy_ctl1 = pphy_desc[phy_id].ctl1;
phy->phy_ctl2 = pphy_desc[phy_id].ctl2;
phy->phy_ctl3 = pphy_desc[phy_id].ctl3;
if (phy->phy_state == NVRAM_PHY_HIDDEN) {
asd->hw_profile.enabled_phys &= ~(1 << phy_id);
}
}
asd_free_mem(pphy_desc);
exit:
return;
}
/*
* Function:
* asd_hwi_get_nv_conn_info
*
* Description:
* This routine reads the Connector Map information from Flash (NVRAM)
* and allocates memory and populates the parameters 'pconn'
* and 'pnoded' with the read information.
*
* At the end of this routine if everything goes fine the data structure
* layout pointed to by 'pconn' and 'pnoded' will be:
*
* 'pconn' ->
* |-----------|--------------|--------------|--------
* | Connector | Connector | Connector | ...
* | Map | Descriptor 0 | Descriptor 1 |
* |-----------|--------------|--------------|--------
*
* 'pnoded' ->
* |--------|--------|--------|--- --|-------|--------|--------|----
* | Node | Phy | Phy |... | Node | Phy | Phy | ...
* | Desc 0 | Desc 0 | Desc 1 | | Desc 1| Desc 0 | Desc 1 |
* |--------|--------|--------|--- --|-------|--------|--------|----
*
* 'pconn_size' will hold the size of data pointed to by 'pconn'
* 'pnoded_size' will hold the size of data pointed to by 'pnoded'.
*
*/
int
asd_hwi_get_nv_conn_info(struct asd_softc *asd,
uint8_t **pconn,
uint32_t *pconn_size,
uint8_t **pnoded,
uint32_t *pnoded_size)
{
struct asd_manuf_base_seg_layout manuf_layout;
struct asd_conn_map_format conn_map;
struct asd_node_desc_format node_desc;
//struct asd_conn_desc_format *pconn_desc;
uint8_t *pconn_buf;
uint8_t *pnode_buf;
uint32_t offset, cur_offset;
uint32_t bytes_to_read, bytes_read;
uint32_t bytes_count, tot_count;
uint32_t node_num;
if (pconn == NULL || pnoded == NULL || pconn_size == NULL
|| pnoded_size == NULL) {
return -1;
}
if (asd_hwi_verify_nv_checksum(asd, NVRAM_MANUF_TYPE,
(uint8_t *) &manuf_layout,
sizeof(manuf_layout))
!= 0) {
asd_log(ASD_DBG_ERROR, "Failed verifying checksum for "
"NVRAM MANUFACTURING LAYOUT.\n");
return -1;
}
/*
* Determine the memory size to be allocated by reading
* the connector_map first
*/
offset = 0;
memset(&conn_map, 0x0, sizeof(conn_map));
if (asd_hwi_get_nv_manuf_seg(asd, &conn_map,
sizeof(conn_map), &offset,
NVRAM_MNF_CONN_MAP) != 0){
return (-1);
}
bytes_to_read = sizeof(conn_map)
+ conn_map.num_conn_desc * conn_map.conn_desc_size;
/*
* Now read connector_map and associated connector_decriptor entries
*/
*pconn_size = bytes_to_read;
if ((pconn_buf = asd_alloc_mem(bytes_to_read, GFP_ATOMIC))
== NULL) {
return (-1);
}
memset(pconn_buf, 0, bytes_to_read);
if (asd_hwi_read_nv_segment(asd, NVRAM_MANUF_TYPE,
pconn_buf, offset,
bytes_to_read,
&bytes_read) != 0) {
asd_free_mem(pconn_buf);
return (-1);
}
/* bypass all read connector_map & connector_descriptor entries */
offset += (bytes_read + 1);
/* no field in connector map yet */
bytes_to_read = sizeof(node_desc);
/*
* Determine memory to be allocated for reading node descriptors
* and their associated phy descriptor entries
*/
bytes_count = 0;
tot_count = 0;
cur_offset = offset;
for (node_num = 0; node_num < conn_map.num_node_desc; node_num++) {
if (asd_hwi_read_nv_segment(asd, NVRAM_MANUF_TYPE,
&node_desc, cur_offset,
bytes_to_read,
&bytes_read) != 0) {
asd_free_mem(pconn_buf);
return (-1);
}
bytes_count = (sizeof(node_desc)
+ (node_desc.num_phy_desc
* node_desc.phy_desc_size));
cur_offset += bytes_count;
tot_count += bytes_count;
}
bytes_to_read = tot_count;
/*
* Now read node descriptors and their
* associated phy descriptor entries
*/
if ((pnode_buf = asd_alloc_mem(bytes_to_read, GFP_ATOMIC))
== NULL) {
asd_free_mem(pconn_buf);
return (-1);
}
if (asd_hwi_read_nv_segment(asd, NVRAM_MANUF_TYPE,
pnode_buf, offset,
bytes_to_read,
&bytes_read) != 0) {
asd_free_mem(pconn_buf);
asd_free_mem(pnode_buf);
return (-1);
}
/* Caller has to free the resources */
*pconn = pconn_buf;
*pnoded = pnode_buf;
*pnoded_size = tot_count;
return 0;
}
static int
asd_hwi_get_nv_manuf_seg(struct asd_softc *asd, void *dest,
uint32_t bytes_to_read, uint32_t *src_offset,
uint16_t signature)
{
struct asd_manuf_base_seg_layout manuf_layout;
uint32_t offset;
uint32_t bytes_read;
int segments_size;
int segment_off;
int err;
memset(&manuf_layout, 0x0, sizeof(manuf_layout));
err = -1;
offset = 0;
/* Retrieve Manufacturing Base segment */
if (asd_hwi_read_nv_segment(asd, NVRAM_MANUF_TYPE, &manuf_layout,
offset, sizeof(manuf_layout),
&bytes_read) != 0) {
return err;
}
/* Retrieve Manufacturing segment specified by signature */
offset = manuf_layout.seg_sign.next_seg_ptr;
segments_size = manuf_layout.sector_size - sizeof(manuf_layout);
segment_off = offset;
while (1) {
if (asd_hwi_read_nv_segment(asd, NVRAM_MANUF_TYPE,
dest, offset, bytes_to_read,
&bytes_read) != 0) {
return (-1);
}
if (((struct asd_manuf_seg_sign *) dest)->signature ==
signature) {
*src_offset = offset;
err = 0;
break;
}
/*
* If next_seg_ptr is 0 then it indicates the last segment.
*/
if (((struct asd_manuf_seg_sign *) dest)->next_seg_ptr == 0)
break;
offset = ((struct asd_manuf_seg_sign *) dest)->next_seg_ptr;
}
return err;
}
static int
asd_hwi_map_lrate_from_sas(u_int sas_link_rate,
u_int *asd_link_rate)
{
switch (sas_link_rate) {
case SAS_RATE_30GBPS:
*asd_link_rate = SAS_30GBPS_RATE;
break;
case SAS_RATE_15GBPS:
*asd_link_rate = SAS_15GBPS_RATE;
break;
default:
return -1;
}
return 0;
}
static int
asd_hwi_set_speed_mask(u_int asd_link_rate,
uint8_t *asd_speed_mask)
{
switch (asd_link_rate) {
case SAS_60GBPS_RATE:
*asd_speed_mask &= ~SAS_SPEED_60_DIS;
break;
case SAS_15GBPS_RATE:
*asd_speed_mask &= ~SAS_SPEED_15_DIS;
break;
case SAS_30GBPS_RATE:
default:
*asd_speed_mask &= ~SAS_SPEED_30_DIS;
break;
}
return 0;
}
/***************************************************************************
* OCM directory default
***************************************************************************/
static struct asd_ocm_dir_format OCMDirInit =
{
OCM_DIR_SIGN, /* signature */
0, /* reserve byte */
0, /* reserve byte */
0, /* Major Version No. */
0, /* Minor Version No. */
0, /* reserve byte */
0x05, /* no. of directory entries */
};
/***************************************************************************
* OCM directory Entries default
***************************************************************************/
static struct asd_ocm_entry_format OCMDirEntriesInit[5] =
{
{
(uint8_t)(OCM_DE_ADDC2C_RES0), /* Entry type */
{
128, /* Offset 0 */
0, /* Offset 1 */
0, /* Offset 2 */
},
0, /* reserve byte */
{
0, /* size 0 */
4, /* size 1 */
0 /* size 2 */
}
},
{
(uint8_t)(OCM_DE_ADDC2C_RES1), /* Entry type */
{
128, /* Offset 0 */
4, /* Offset 1 */
0, /* Offset 2 */
},
0, /* reserve byte */
{
0, /* size 0 */
4, /* size 1 */
0 /* size 2 */
}
},
{
(uint8_t)(OCM_DE_ADDC2C_RES2), /* Entry type */
{
128, /* Offset 0 */
8, /* Offset 1 */
0, /* Offset 2 */
},
0, /* reserve byte */
{
0, /* size 0 */
4, /* size 1 */
0 /* size 2 */
}
},
{
(uint8_t)(OCM_DE_ADDC2C_RES3), /* Entry type */
{
128, /* Offset 0 */
12, /* Offset 1 */
0, /* Offset 2 */
},
0, /* reserve byte */
{
0, /* size 0 */
4, /* size 1 */
0 /* size 2 */
}
},
{
(uint8_t)(OCM_DE_WIN_DRVR), /* Entry type */
{
128, /* Offset 0 */
16, /* Offset 1 */
0, /* Offset 2 */
},
0, /* reserve byte */
{
128, /* size 0 (125824 % 256) */
235, /* size 1 (125824 / 256) */
1 /* size 2 (125824 /(256 * 256)) */
}
}
};
static int
asd_hwi_initialize_ocm_dir (struct asd_softc *asd)
{
uint8_t *pOCMData;
uint8_t i;
/* load the OCM directory format from OCMDirInit data */
pOCMData = (uint8_t *) &OCMDirInit;
for (i = 0; i < sizeof(struct asd_ocm_dir_format); i++)
{
asd_hwi_swb_write_byte(asd, OCM_BASE_ADDR + i, pOCMData[i]);
}
/* load the OCM directory format from OCMDirInit data */
pOCMData = (uint8_t *) &OCMDirEntriesInit[0];
for (i = 0; i < (sizeof(struct asd_ocm_entry_format) * 5); i++)
{
asd_hwi_swb_write_byte(asd, OCM_BASE_ADDR + (i + sizeof(struct asd_ocm_dir_format)), pOCMData[i]);
}
return 0;
}
static int
asd_hwi_check_ocm_access (struct asd_softc *asd)
{
uint32_t exsi_base_addr;
uint32_t reg_contents;
uint32_t i;
uint32_t intrptStatus;
/* check if OCM has been initialized by BIOS */
exsi_base_addr = EXSI_REG_BASE_ADR + EXSICNFGR;
reg_contents = asd_hwi_swb_read_dword(asd, exsi_base_addr);
#ifdef ASD_DEBUG
asd_log(ASD_DBG_INFO, "Current EXSICNFGR is 0x%x\n",reg_contents);
#endif
if (!(reg_contents & OCMINITIALIZED)) {
intrptStatus = asd_pcic_read_dword(asd,PCIC_INTRPT_STAT);
#ifdef ASD_DEBUG
asd_log(ASD_DBG_INFO, "OCM is not initialized by BIOS, reinitialize it and ignore it, current IntrptStatus is 0x%x\n",intrptStatus);
#endif
/* Initialize OCM to avoid future OCM access to get parity error */
/* clear internal error register */
asd_pcic_write_dword(asd, PCIC_INTRPT_STAT, intrptStatus);
for (i = 0; i < OCM_MAX_SIZE; i += 4)
{
asd_hwi_swb_write_dword(asd, OCM_BASE_ADDR + i, 0);
}
asd_hwi_initialize_ocm_dir(asd);
return -1;
}
return 0;
}
static int
asd_hwi_get_ocm_info(struct asd_softc *asd)
{
struct asd_ocm_entry_format ocm_de;
struct asd_bios_chim_format *pbios_chim;
uint32_t offset, bytes_read, bytes_to_read;
if(asd_hwi_check_ocm_access(asd) != 0) {
return -1;
}
if (asd_hwi_get_ocm_entry(asd, OCM_DE_BIOS_CHIM,
&ocm_de, &offset) != 0) {
return -1;
}
bytes_to_read = OCM_DE_OFFSET_SIZE_CONV(ocm_de.size);
if ((pbios_chim = asd_alloc_mem(bytes_to_read, GFP_ATOMIC))
== NULL) {
return (-1);
}
if (asd_hwi_read_ocm_seg(asd, pbios_chim,
OCM_DE_OFFSET_SIZE_CONV(ocm_de.offset),
bytes_to_read,
&bytes_read) != 0) {
asd_free_mem(pbios_chim);
return -1;
}
if (pbios_chim->signature == OCM_BC_BIOS_SIGN) {
if (pbios_chim->bios_present
& OCM_BC_BIOS_PRSNT_MASK) {
asd->hw_profile.bios_maj_ver =
pbios_chim->bios_maj_ver;
asd->hw_profile.bios_min_ver =
pbios_chim->bios_min_ver;
asd->hw_profile.bios_bld_num =
pbios_chim->bios_bld_num;
}
}
asd->unit_elements = asd_alloc_mem(pbios_chim->num_elements *
sizeof(struct asd_unit_element_format), GFP_ATOMIC);
if (asd->unit_elements == NULL) {
asd_free_mem(pbios_chim);
return 0;
}
asd->num_unit_elements = pbios_chim->num_elements;
memcpy(asd->unit_elements, &pbios_chim->unit_elm[0],
pbios_chim->num_elements *
sizeof(struct asd_unit_element_format));
asd_free_mem(pbios_chim);
return 0;
}
static int
asd_hwi_get_ocm_entry(struct asd_softc *asd,
uint32_t entry_type,
struct asd_ocm_entry_format *pocm_de,
uint32_t *src_offset)
{
struct asd_ocm_dir_format ocm_dir;
uint32_t offset, entry_no;
u_int bytes_read;
int err;
memset(&ocm_dir, 0x0, sizeof (ocm_dir));
memset(pocm_de, 0x0, sizeof (*pocm_de));
offset = 0;
err = -1;
if (asd_hwi_read_ocm_seg(asd, &ocm_dir, offset,
sizeof(ocm_dir), &bytes_read)) {
return -1;
}
if ((ocm_dir.signature != OCM_DIR_SIGN)
/*|| ((ocm_dir.num_entries & OCM_NUM_ENTRIES_MASK) == 0)*/) {
return -1;
}
offset = sizeof(ocm_dir);
for (entry_no = 0;
entry_no < (ocm_dir.num_entries & OCM_NUM_ENTRIES_MASK);
entry_no++, offset += sizeof(*pocm_de)) {
if (asd_hwi_read_ocm_seg(asd, pocm_de, offset,
sizeof(*pocm_de), &bytes_read)) {
return -1;
}
if (pocm_de->type == entry_type) {
err = 0;
break;
}
}
*src_offset = offset;
return err;
}
static int
asd_hwi_read_ocm_seg(struct asd_softc *asd, void *dest,
uint32_t src_offset, u_int bytes_to_read,
u_int *bytes_read)
{
uint8_t *dest_buf;
uint32_t nv_offset;
uint32_t i;
nv_offset = 0;
nv_offset = OCM_BASE_ADDR + nv_offset + src_offset;
dest_buf = (uint8_t *) dest;
*bytes_read = 0;
for (i = 0; i < bytes_to_read; i++) {
*(dest_buf+i) = asd_hwi_swb_read_byte(asd, (nv_offset + i));
}
*bytes_read = i - 1;
return (0);
}
static int asd_hwi_check_flash(struct asd_softc *asd)
{
uint32_t nv_flash_bar;
uint32_t exsi_base_addr;
uint32_t reg_contents;
uint8_t manuf_id;
uint8_t dev_id_boot_blk;
uint8_t sec_prot;
/* get Flash memory base address */
asd->hw_profile.nv_flash_bar =
asd_pcic_read_dword(asd, PCIC_FLASH_MBAR);
nv_flash_bar = asd->hw_profile.nv_flash_bar;
/* check presence of flash */
exsi_base_addr = EXSI_REG_BASE_ADR + EXSICNFGR;
reg_contents = asd_hwi_swb_read_dword(asd, exsi_base_addr);
if (!(reg_contents & FLASHEX)) {
asd->hw_profile.flash_present = FALSE;
return -1;
}
asd->hw_profile.flash_present = TRUE;
/* Determine flash info */
if (asd_hwi_reset_nvram(asd) != 0) {
return (-1);
}
asd->hw_profile.flash_method = FLASH_METHOD_UNKNOWN;
asd->hw_profile.flash_manuf_id = FLASH_MANUF_ID_UNKNOWN;
asd->hw_profile.flash_dev_id = FLASH_DEV_ID_UNKNOWN;
/*
* The strategy is to try to read the flash ID using "Method A" first.
* If that fails, we will try "Method B"
*/
/* Issue Unlock sequence for AM29LV800D */
asd_hwi_swb_write_byte(asd, (nv_flash_bar + 0xAAA), 0xAA);
asd_hwi_swb_write_byte(asd, (nv_flash_bar + 0x555), 0x55);
/* Issue the erase command */
asd_hwi_swb_write_byte(asd, (nv_flash_bar + 0xAAA), 0x90);
manuf_id = asd_hwi_swb_read_byte(asd, nv_flash_bar);
dev_id_boot_blk = asd_hwi_swb_read_byte(asd, nv_flash_bar + 1);
sec_prot = asd_hwi_swb_read_byte(asd, nv_flash_bar + 2);
#ifdef ASD_DEBUG
asd_log(ASD_DBG_INFO, "Flash MethodA manuf_id(0x%x) dev_id_boot_blk(0x%x) sec_prot(0x%x)\n",manuf_id,dev_id_boot_blk,sec_prot);
#endif
if (asd_hwi_reset_nvram(asd) != 0) {
return (-1);
}
switch (manuf_id) {
case FLASH_MANUF_ID_AMD:
switch (sec_prot) {
case FLASH_DEV_ID_AM29LV800DT:
case FLASH_DEV_ID_AM29LV640MT:
asd->hw_profile.flash_method = FLASH_METHOD_A;
break;
default:
break;
}
break;
case FLASH_MANUF_ID_ST:
switch (sec_prot) {
case FLASH_DEV_ID_STM29W800DT:
asd->hw_profile.flash_method = FLASH_METHOD_A;
break;
default:
break;
}
break;
case FLASH_MANUF_ID_FUJITSU:
switch (sec_prot) {
case FLASH_DEV_ID_MBM29LV800TE:
asd->hw_profile.flash_method = FLASH_METHOD_A;
break;
}
break;
case FLASH_MANUF_ID_MACRONIX:
switch (sec_prot) {
case FLASH_DEV_ID_MX29LV800BT:
asd->hw_profile.flash_method = FLASH_METHOD_A;
break;
}
break;
}
if (asd->hw_profile.flash_method == FLASH_METHOD_UNKNOWN) {
if (asd_hwi_reset_nvram(asd) != 0) {
return (-1);
}
/* Issue Unlock sequence for AM29LV008BT */
asd_hwi_swb_write_byte(asd, (nv_flash_bar + 0x555), 0xAA);
asd_hwi_swb_write_byte(asd, (nv_flash_bar + 0x2AA), 0x55);
asd_hwi_swb_write_byte(asd, (nv_flash_bar + 0x555), 0x90);
manuf_id = asd_hwi_swb_read_byte(asd, nv_flash_bar);
dev_id_boot_blk = asd_hwi_swb_read_byte(asd, nv_flash_bar + 1);
sec_prot = asd_hwi_swb_read_byte(asd, nv_flash_bar + 2);
#ifdef ASD_DEBUG
asd_log(ASD_DBG_INFO, "Flash MethodB manuf_id(0x%x) dev_id_boot_blk(0x%x) sec_prot(0x%x)\n",manuf_id,dev_id_boot_blk,sec_prot);
#endif
if (asd_hwi_reset_nvram(asd) != 0) {
return (-1);
}
switch (manuf_id) {
case FLASH_MANUF_ID_AMD:
switch (dev_id_boot_blk) {
case FLASH_DEV_ID_AM29LV008BT:
asd->hw_profile.flash_method = FLASH_METHOD_B;
break;
default:
break;
}
break;
case FLASH_MANUF_ID_FUJITSU:
switch (dev_id_boot_blk) {
case FLASH_DEV_ID_MBM29LV008TA:
asd->hw_profile.flash_method = FLASH_METHOD_B;
break;
}
break;
default:
return -1;
}
}
switch (asd->hw_profile.flash_method)
{
case FLASH_METHOD_A:
return 0;
case FLASH_METHOD_B:
break;
default:
return -1;
}
asd->hw_profile.flash_manuf_id = manuf_id;
asd->hw_profile.flash_dev_id = dev_id_boot_blk;
asd->hw_profile.flash_wr_prot = sec_prot;
return 0;
}
#endif /* NVRAM_SUPPORT */
int
asd_hwi_control_activity_leds(struct asd_softc *asd, uint8_t phy_id,
uint32_t asd_phy_ctl_func)
{
uint32_t exsi_base_addr;
uint32_t reg_contents;
uint32_t reg_data;
//JD we support B0,B1...
// if (asd->hw_profile.rev_id != AIC9410_DEV_REV_B0)
// return -EINVAL;
if (phy_id >= ASD_MAX_XDEVLED_BITS)
return -EINVAL;
reg_data = 0;
/* set the bit map corresponding to phy_id */
reg_data = (1 << phy_id);
/* Enable/Disable activity LED for the PHY */
exsi_base_addr = EXSI_REG_BASE_ADR + GPIOOER;
reg_contents = asd_hwi_swb_read_dword(asd, exsi_base_addr);
if (asd_phy_ctl_func == DISABLE_PHY) {
reg_contents &= ~reg_data;
} else {
if (asd_phy_ctl_func == ENABLE_PHY
|| asd_phy_ctl_func == ENABLE_PHY_NO_SAS_OOB
|| asd_phy_ctl_func == ENABLE_PHY_NO_SATA_OOB ) {
reg_contents |= reg_data;
}
}
asd_hwi_swb_write_dword(asd, exsi_base_addr, reg_contents);
/* Set activity source to external/internal */
exsi_base_addr = EXSI_REG_BASE_ADR + GPIOCNFGR;
reg_contents = asd_hwi_swb_read_dword(asd, exsi_base_addr);
if (asd_phy_ctl_func == DISABLE_PHY) {
reg_contents &= ~reg_data;
} else {
if (asd_phy_ctl_func == ENABLE_PHY
|| asd_phy_ctl_func == ENABLE_PHY_NO_SAS_OOB
|| asd_phy_ctl_func == ENABLE_PHY_NO_SATA_OOB ) {
reg_contents |= reg_data;
}
}
asd_hwi_swb_write_dword(asd, exsi_base_addr, reg_contents);
return 0;
}
|