/*******************************************************************************
Intel(R) Gigabit Ethernet Linux driver
Copyright(c) 2007-2009 Intel Corporation.
Copyright(c) 2007-2013 Intel Corporation.
This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License,
@@ -31,57 +31,125 @@
* 82575GB Gigabit Network Connection
* 82576 Gigabit Network Connection
* 82576 Quad Port Gigabit Mezzanine Adapter
* 82580 Gigabit Network Connection
* I350 Gigabit Network Connection
*/
#include "e1000_api.h"
#include "e1000_i210.h"
static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw);
static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
static s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
static void e1000_release_phy_82575(struct e1000_hw *hw);
static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
static void e1000_release_nvm_82575(struct e1000_hw *hw);
static s32 e1000_check_for_link_82575(struct e1000_hw *hw);
static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw);
static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
u16 *duplex);
static s32 e1000_init_hw_82575(struct e1000_hw *hw);
static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
u16 *data);
static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
static s32 e1000_reset_hw_82580(struct e1000_hw *hw);
static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
u32 offset, u16 *data);
static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
u32 offset, u16 data);
static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
bool active);
static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
static s32 e1000_get_media_type_82575(struct e1000_hw *hw);
static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
u16 *speed, u16 *duplex);
static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
static const u16 e1000_82580_rxpbs_table[] =
{ 36, 72, 144, 1, 2, 4, 8, 16,
35, 70, 140 };
static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
u16 offset);
static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
static void e1000_clear_vfta_i350(struct e1000_hw *hw);
static void e1000_i2c_start(struct e1000_hw *hw);
static void e1000_i2c_stop(struct e1000_hw *hw);
static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
static bool e1000_get_i2c_data(u32 *i2cctl);
static const u16 e1000_82580_rxpbs_table[] = {
36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
#define E1000_82580_RXPBS_TABLE_SIZE \
(sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
/**
* e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
* @hw: pointer to the HW structure
*
* Called to determine if the I2C pins are being used for I2C or as an
* external MDIO interface since the two options are mutually exclusive.
**/
static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
{
u32 reg = 0;
bool ext_mdio = false;
DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
switch (hw->mac.type) {
case e1000_82575:
case e1000_82576:
reg = E1000_READ_REG(hw, E1000_MDIC);
ext_mdio = !!(reg & E1000_MDIC_DEST);
break;
case e1000_82580:
case e1000_i350:
case e1000_i354:
case e1000_i210:
case e1000_i211:
reg = E1000_READ_REG(hw, E1000_MDICNFG);
ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
default:
}
return ext_mdio;
* e1000_init_phy_params_82575 - Init PHY func ptrs.
@@ -90,9 +158,13 @@ static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
struct e1000_phy_info *phy = &hw->phy;
s32 ret_val = E1000_SUCCESS;
u32 ctrl_ext;
DEBUGFUNC("e1000_init_phy_params_82575");
phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
if (hw->phy.media_type != e1000_media_type_copper) {
phy->type = e1000_phy_none;
goto out;
@@ -101,27 +173,48 @@ static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
phy->ops.power_up = e1000_power_up_phy_copper;
phy->ops.power_down = e1000_power_down_phy_copper_82575;
phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
phy->reset_delay_us = 100;
phy->ops.acquire = e1000_acquire_phy_82575;
phy->ops.check_reset_block = e1000_check_reset_block_generic;
phy->ops.commit = e1000_phy_sw_reset_generic;
phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
phy->ops.release = e1000_release_phy_82575;
ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
if (e1000_sgmii_active_82575(hw)) {
phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
} else if (hw->mac.type >= e1000_82580) {
phy->ops.reset = e1000_phy_hw_reset_generic;
phy->ops.read_reg = e1000_read_phy_reg_82580;
phy->ops.write_reg = e1000_write_phy_reg_82580;
ctrl_ext |= E1000_CTRL_I2C_ENA;
} else {
ctrl_ext &= ~E1000_CTRL_I2C_ENA;
E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
e1000_reset_mdicnfg_82580(hw);
if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
phy->ops.read_reg = e1000_read_phy_reg_igp;
phy->ops.write_reg = e1000_write_phy_reg_igp;
phy->ops.read_reg = e1000_read_phy_reg_gs40g;
phy->ops.write_reg = e1000_write_phy_reg_gs40g;
/* Set phy->phy_addr and phy->id. */
@@ -129,30 +222,78 @@ static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
/* Verify phy id and set remaining function pointers */
switch (phy->id) {
case M88E1543_E_PHY_ID:
case I347AT4_E_PHY_ID:
case M88E1112_E_PHY_ID:
case M88E1340M_E_PHY_ID:
case M88E1111_I_PHY_ID:
phy->type = e1000_phy_m88;
phy->ops.check_polarity = e1000_check_polarity_m88;
phy->ops.get_info = e1000_get_phy_info_m88;
phy->ops.get_cable_length = e1000_get_cable_length_m88;
if (phy->id == I347AT4_E_PHY_ID ||
phy->id == M88E1112_E_PHY_ID ||
phy->id == M88E1340M_E_PHY_ID)
phy->ops.get_cable_length =
e1000_get_cable_length_m88_gen2;
else if (phy->id == M88E1543_E_PHY_ID)
else
phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
/* Check if this PHY is confgured for media swap. */
if (phy->id == M88E1112_E_PHY_ID) {
u16 data;
ret_val = phy->ops.write_reg(hw,
E1000_M88E1112_PAGE_ADDR,
2);
if (ret_val)
ret_val = phy->ops.read_reg(hw,
E1000_M88E1112_MAC_CTRL_1,
&data);
data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
data == E1000_M88E1112_AUTO_COPPER_BASEX)
hw->mac.ops.check_for_link =
e1000_check_for_link_media_swap;
case IGP03E1000_E_PHY_ID:
case IGP04E1000_E_PHY_ID:
phy->type = e1000_phy_igp_3;
phy->ops.check_polarity = e1000_check_polarity_igp;
phy->ops.get_info = e1000_get_phy_info_igp;
phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
case I82580_I_PHY_ID:
case I350_I_PHY_ID:
phy->type = e1000_phy_82580;
phy->ops.check_polarity = e1000_check_polarity_82577;
phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82577;
phy->ops.get_cable_length = e1000_get_cable_length_82577;
phy->ops.get_info = e1000_get_phy_info_82577;
phy->ops.force_speed_duplex =
e1000_phy_force_speed_duplex_82577;
phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
case I210_I_PHY_ID:
phy->type = e1000_phy_i210;
phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
ret_val = -E1000_ERR_PHY;
@@ -167,7 +308,7 @@ out:
* e1000_init_nvm_params_82575 - Init NVM func ptrs.
static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
struct e1000_nvm_info *nvm = &hw->nvm;
u32 eecd = E1000_READ_REG(hw, E1000_EECD);
@@ -175,47 +316,75 @@ static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
DEBUGFUNC("e1000_init_nvm_params_82575");
nvm->opcode_bits = 8;
nvm->delay_usec = 1;
switch (nvm->override) {
case e1000_nvm_override_spi_large:
nvm->page_size = 32;
nvm->address_bits = 16;
case e1000_nvm_override_spi_small:
nvm->page_size = 8;
nvm->address_bits = 8;
nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
nvm->type = e1000_nvm_eeprom_spi;
size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
E1000_EECD_SIZE_EX_SHIFT);
/*
* Added to a constant, "size" becomes the left-shift value
* for setting word_size.
size += NVM_WORD_SIZE_BASE_SHIFT;
/* EEPROM access above 16k is unsupported */
if (size > 14)
size = 14;
/* Just in case size is out of range, cap it to the largest
* EEPROM size supported
if (size > 15)
size = 15;
nvm->word_size = 1 << size;
if (hw->mac.type < e1000_i210) {
nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
16 : 8;
if (nvm->word_size == (1 << 15))
nvm->page_size = 128;
nvm->type = e1000_nvm_flash_hw;
/* Function Pointers */
nvm->ops.acquire = e1000_acquire_nvm_82575;
nvm->ops.read = e1000_read_nvm_eerd;
nvm->ops.release = e1000_release_nvm_82575;
nvm->ops.update = e1000_update_nvm_checksum_generic;
if (nvm->word_size < (1 << 15))
nvm->ops.read = e1000_read_nvm_spi;
nvm->ops.write = e1000_write_nvm_spi;
nvm->ops.validate = e1000_validate_nvm_checksum_generic;
nvm->ops.valid_led_default = e1000_valid_led_default_82575;
/* override generic family function pointers for specific descendants */
nvm->ops.validate = e1000_validate_nvm_checksum_82580;
nvm->ops.update = e1000_update_nvm_checksum_82580;
nvm->ops.validate = e1000_validate_nvm_checksum_i350;
nvm->ops.update = e1000_update_nvm_checksum_i350;
return E1000_SUCCESS;
@@ -228,46 +397,11 @@ static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
struct e1000_mac_info *mac = &hw->mac;
struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
u32 ctrl_ext = 0;
DEBUGFUNC("e1000_init_mac_params_82575");
/* Set media type */
* The 82575 uses bits 22:23 for link mode. The mode can be changed
* based on the EEPROM. We cannot rely upon device ID. There
* is no distinguishable difference between fiber and internal
* SerDes mode on the 82575. There can be an external PHY attached
* on the SGMII interface. For this, we'll set sgmii_active to true.
hw->phy.media_type = e1000_media_type_copper;
dev_spec->sgmii_active = false;
switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
case E1000_CTRL_EXT_LINK_MODE_SGMII:
dev_spec->sgmii_active = true;
case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
hw->phy.media_type = e1000_media_type_internal_serdes;
* if using i2c make certain the MDICNFG register is cleared to prevent
* communications from being misrouted to the mdic registers
if ((ctrl_ext & E1000_CTRL_I2C_ENA) && (hw->mac.type == e1000_82580))
E1000_WRITE_REG(hw, E1000_MDICNFG, 0);
/* Derives media type */
e1000_get_media_type_82575(hw);
/* Set mta register count */
mac->mta_reg_count = 128;
/* Set uta register count */
@@ -278,21 +412,31 @@ static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
if (mac->type == e1000_82580)
mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
if (mac->type == e1000_i350)
if (mac->type == e1000_i350 || mac->type == e1000_i354)
mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
/* Enable EEE default settings for EEE supported devices */
if (mac->type >= e1000_i350)
dev_spec->eee_disable = false;
/* Allow a single clear of the SW semaphore on I210 and newer */
if (mac->type >= e1000_i210)
dev_spec->clear_semaphore_once = true;
/* Set if part includes ASF firmware */
mac->asf_firmware_present = true;
/* Set if manageability features are enabled. */
/* FWSM register */
mac->has_fwsm = true;
/* ARC supported; valid only if manageability features are enabled. */
mac->arc_subsystem_valid =
(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
? true : false;
!!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
/* Function pointers */
/* bus type/speed/width */
mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
/* reset */
if (mac->type >= e1000_82580)
mac->ops.reset_hw = e1000_reset_hw_82580;
mac->ops.reset_hw = e1000_reset_hw_82575;
@@ -302,25 +446,34 @@ static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
mac->ops.setup_link = e1000_setup_link_generic;
/* physical interface link setup */
mac->ops.setup_physical_interface =
(hw->phy.media_type == e1000_media_type_copper)
? e1000_setup_copper_link_82575
: e1000_setup_serdes_link_82575;
? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
/* physical interface shutdown */
mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
/* physical interface power up */
mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
/* check for link */
mac->ops.check_for_link = e1000_check_for_link_82575;
/* receive address register setting */
mac->ops.rar_set = e1000_rar_set_generic;
/* read mac address */
mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
/* configure collision distance */
mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
/* multicast address update */
mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
/* writing VFTA */
mac->ops.write_vfta = e1000_write_vfta_generic;
/* clearing VFTA */
mac->ops.clear_vfta = e1000_clear_vfta_generic;
/* setting MTA */
mac->ops.mta_set = e1000_mta_set_generic;
if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
mac->ops.write_vfta = e1000_write_vfta_i350;
mac->ops.clear_vfta = e1000_clear_vfta_i350;
if (hw->mac.type >= e1000_82580)
mac->ops.validate_mdi_setting =
e1000_validate_mdi_setting_crossover_generic;
/* ID LED init */
mac->ops.id_led_init = e1000_id_led_init_generic;
/* blink LED */
@@ -336,6 +489,18 @@ static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
/* link info */
mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
/* get thermal sensor data */
mac->ops.get_thermal_sensor_data =
e1000_get_thermal_sensor_data_generic;
mac->ops.init_thermal_sensor_thresh =
e1000_init_thermal_sensor_thresh_generic;
/* acquire SW_FW sync */
mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
if (mac->type >= e1000_i210) {
mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
/* set lan id for port to determine which phy lock to use */
hw->mac.ops.set_lan_id(hw);
@@ -378,7 +543,7 @@ static s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
else if (hw->bus.func == E1000_FUNC_3)
mask = E1000_SWFW_PHY3_SM;
return e1000_acquire_swfw_sync_82575(hw, mask);
return hw->mac.ops.acquire_swfw_sync(hw, mask);
@@ -400,7 +565,7 @@ static void e1000_release_phy_82575(struct e1000_hw *hw)
e1000_release_swfw_sync_82575(hw, mask);
hw->mac.ops.release_swfw_sync(hw, mask);
@@ -413,7 +578,7 @@ static void e1000_release_phy_82575(struct e1000_hw *hw)
* interface and stores the retrieved information in data.
u16 *data)
s32 ret_val = -E1000_ERR_PARAM;
@@ -446,7 +611,7 @@ out:
* media independent interface.
static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
u16 data)
@@ -482,6 +647,7 @@ static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
u16 phy_id;
u32 mdic;
DEBUGFUNC("e1000_get_phy_id_82575");
@@ -498,10 +664,36 @@ static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
if (e1000_sgmii_uses_mdio_82575(hw)) {
mdic = E1000_READ_REG(hw, E1000_MDIC);
mdic &= E1000_MDIC_PHY_MASK;
phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
mdic = E1000_READ_REG(hw, E1000_MDICNFG);
mdic &= E1000_MDICNFG_PHY_MASK;
phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
ret_val = e1000_get_phy_id(hw);
/* Power on sgmii phy if it is disabled */
E1000_WRITE_REG(hw, E1000_CTRL_EXT,
ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
E1000_WRITE_FLUSH(hw);
msec_delay(300);
@@ -513,8 +705,7 @@ static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
if (ret_val == E1000_SUCCESS) {
DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
phy_id,
phy->addr);
phy_id, phy->addr);
* At the time of this writing, The M88 part is
* the only supported SGMII PHY product.
@@ -523,7 +714,7 @@ static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
DEBUGOUT1("PHY address %u was unreadable\n",
@@ -609,22 +800,22 @@ static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
if (active) {
data |= IGP02E1000_PM_D0_LPLU;
ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
data);
/* When LPLU is enabled, we should disable SmartSpeed */
ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
data &= ~IGP02E1000_PM_D0_LPLU;
* LPLU and SmartSpeed are mutually exclusive. LPLU is used
* during Dx states where the power conservation is most
@@ -633,28 +824,28 @@ static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
if (phy->smart_speed == e1000_smart_speed_on) {
IGP01E1000_PHY_PORT_CONFIG,
data |= IGP01E1000_PSCFR_SMART_SPEED;
} else if (phy->smart_speed == e1000_smart_speed_off) {
@@ -664,6 +855,101 @@ out:
return ret_val;
* e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
* @active: true to enable LPLU, false to disable
* Sets the LPLU D0 state according to the active flag. When
* activating LPLU this function also disables smart speed
* and vice versa. LPLU will not be activated unless the
* device autonegotiation advertisement meets standards of
* either 10 or 10/100 or 10/100/1000 at all duplexes.
* This is a function pointer entry point only called by
* PHY setup routines.
static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
u32 data;
DEBUGFUNC("e1000_set_d0_lplu_state_82580");
data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
data |= E1000_82580_PM_D0_LPLU;
data &= ~E1000_82580_PM_SPD;
data &= ~E1000_82580_PM_D0_LPLU;
* important. During driver activity we should enable
* SmartSpeed, so performance is maintained.
if (phy->smart_speed == e1000_smart_speed_on)
data |= E1000_82580_PM_SPD;
else if (phy->smart_speed == e1000_smart_speed_off)
E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
* e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
* @active: boolean used to enable/disable lplu
* Success returns 0, Failure returns 1
* The low power link up (lplu) state is set to the power management level D3
* and SmartSpeed is disabled when active is true, else clear lplu for D3
* and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
* is used during Dx states where the power conservation is most important.
* During driver activity, SmartSpeed should be enabled so performance is
* maintained.
s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
DEBUGFUNC("e1000_set_d3_lplu_state_82580");
if (!active) {
data &= ~E1000_82580_PM_D3_LPLU;
} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
(phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
(phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
data |= E1000_82580_PM_D3_LPLU;
* e1000_acquire_nvm_82575 - Request for access to EEPROM
@@ -683,8 +969,32 @@ static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
ret_val = e1000_acquire_nvm_generic(hw);
* Check if there is some access
* error this access may hook on
if (hw->mac.type == e1000_i350) {
if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
E1000_EECD_TIMEOUT)) {
/* Clear all access error flags */
E1000_WRITE_REG(hw, E1000_EECD, eecd |
E1000_EECD_ERROR_CLR);
DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
if (hw->mac.type == e1000_82580) {
if (eecd & E1000_EECD_BLOCKED) {
/* Clear access error flag */
E1000_EECD_BLOCKED);
e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
@@ -704,6 +1014,7 @@ static void e1000_release_nvm_82575(struct e1000_hw *hw)
DEBUGFUNC("e1000_release_nvm_82575");
e1000_release_nvm_generic(hw);
@@ -773,8 +1084,8 @@ static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
DEBUGFUNC("e1000_release_swfw_sync_82575");
while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS);
/* Empty */
while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
; /* Empty */
swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
swfw_sync &= ~mask;
@@ -817,7 +1128,7 @@ static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
DEBUGOUT("MNG configuration cycle has not completed.\n");
/* If EEPROM is not marked present, init the PHY manually */
if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
(hw->phy.type == e1000_phy_igp_3))
e1000_phy_init_script_igp3(hw);
@@ -835,7 +1146,7 @@ static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
* Otherwise, use the generic function to get the link speed and duplex info.
u16 *duplex)
s32 ret_val;
@@ -843,10 +1154,10 @@ static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
if (hw->phy.media_type != e1000_media_type_copper)
ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
duplex);
ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
@@ -867,13 +1178,23 @@ static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
&duplex);
* Use this flag to determine if link needs to be checked or
* not. If we have link clear the flag so that we do not
* continue to check for link.
hw->mac.get_link_status = !hw->mac.serdes_has_link;
* Configure Flow Control now that Auto-Neg has completed.
* First, we need to restore the desired flow control
* settings because we may have had to re-autoneg with a
* different link partner.
ret_val = e1000_config_fc_after_link_up_generic(hw);
DEBUGOUT("Error configuring flow control\n");
ret_val = e1000_check_for_copper_link_generic(hw);
@@ -881,6 +1202,85 @@ static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
* e1000_check_for_link_media_swap - Check which M88E1112 interface linked
* Poll the M88E1112 interfaces to see which interface achieved link.
static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
u8 port = 0;
DEBUGFUNC("e1000_check_for_link_media_swap");
/* Check the copper medium. */
ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
if (data & E1000_M88E1112_STATUS_LINK)
port = E1000_MEDIA_PORT_COPPER;
/* Check the other medium. */
ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
port = E1000_MEDIA_PORT_OTHER;
/* Determine if a swap needs to happen. */
if (port && (hw->dev_spec._82575.media_port != port)) {
hw->dev_spec._82575.media_port = port;
hw->dev_spec._82575.media_changed = true;
ret_val = e1000_check_for_link_82575(hw);
* e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
u32 reg;
DEBUGFUNC("e1000_power_up_serdes_link_82575");
if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
!e1000_sgmii_active_82575(hw))
return;
/* Enable PCS to turn on link */
reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
reg |= E1000_PCS_CFG_PCS_EN;
E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
/* Power up the laser */
reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
reg &= ~E1000_CTRL_EXT_SDP3_DATA;
E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
/* flush the write to verify completion */
msec_delay(1);
* e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
@@ -891,18 +1291,14 @@ static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
* duplex, then store the values in the pointers provided.
u16 *speed, u16 *duplex)
u32 pcs;
u32 status;
DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
/* Set up defaults for the return values of this function */
mac->serdes_has_link = false;
*speed = 0;
*duplex = 0;
* Read the PCS Status register for link state. For non-copper mode,
* the status register is not accurate. The PCS status register is
@@ -911,28 +1307,41 @@ static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
* The link up bit determines when link is up on autoneg. The sync ok
* gets set once both sides sync up and agree upon link. Stable link
* can be determined by checking for both link up and link sync ok
* The link up bit determines when link is up on autoneg.
if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
if (pcs & E1000_PCS_LSTS_LINK_OK) {
mac->serdes_has_link = true;
/* Detect and store PCS speed */
if (pcs & E1000_PCS_LSTS_SPEED_1000) {
if (pcs & E1000_PCS_LSTS_SPEED_1000)
*speed = SPEED_1000;
} else if (pcs & E1000_PCS_LSTS_SPEED_100) {
else if (pcs & E1000_PCS_LSTS_SPEED_100)
*speed = SPEED_100;
*speed = SPEED_10;
/* Detect and store PCS duplex */
if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
*duplex = FULL_DUPLEX;
*duplex = HALF_DUPLEX;
/* Check if it is an I354 2.5Gb backplane connection. */
if (mac->type == e1000_i354) {
status = E1000_READ_REG(hw, E1000_STATUS);
if ((status & E1000_STATUS_2P5_SKU) &&
!(status & E1000_STATUS_2P5_SKU_OVER)) {
*speed = SPEED_2500;
DEBUGOUT("2500 Mbs, ");
DEBUGOUT("Full Duplex\n");
@@ -948,27 +1357,14 @@ static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
u16 eeprom_data = 0;
DEBUGFUNC("e1000_shutdown_serdes_link_82575");
if (hw->bus.func == E1000_FUNC_0)
hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
else if (hw->mac.type == e1000_82580)
hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
&eeprom_data);
else if (hw->bus.func == E1000_FUNC_1)
hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
* If APM is not enabled in the EEPROM and management interface is
* not enabled, then power down.
if (!(eeprom_data & E1000_NVM_APME_82575) &&
!e1000_enable_mng_pass_thru(hw)) {
if (!e1000_enable_mng_pass_thru(hw)) {
/* Disable PCS to turn off link */
reg &= ~E1000_PCS_CFG_PCS_EN;
@@ -995,7 +1391,7 @@ void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
u32 ctrl, icr;
u32 ctrl;
DEBUGFUNC("e1000_reset_hw_82575");
@@ -1005,15 +1401,13 @@ static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
* on the last TLP read/write transaction when MAC is reset.
ret_val = e1000_disable_pcie_master_generic(hw);
if (ret_val) {
DEBUGOUT("PCI-E Master disable polling has failed.\n");
/* set the completion timeout for interface */
ret_val = e1000_set_pcie_completion_timeout(hw);
DEBUGOUT("PCI-E Set completion timeout has failed.\n");
DEBUGOUT("Masking off all interrupts\n");
E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
@@ -1040,12 +1434,12 @@ static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
/* If EEPROM is not present, run manual init scripts */
if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0)
if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
e1000_reset_init_script_82575(hw);
/* Clear any pending interrupt events. */
icr = E1000_READ_REG(hw, E1000_ICR);
E1000_READ_REG(hw, E1000_ICR);
/* Install any alternate MAC address into RAR0 */
ret_val = e1000_check_alt_mac_addr_generic(hw);
@@ -1094,6 +1488,9 @@ static s32 e1000_init_hw_82575(struct e1000_hw *hw)
/* Setup link and flow control */
ret_val = mac->ops.setup_link(hw);
/* Set the default MTU size */
hw->dev_spec._82575.mtu = 1500;
* Clear all of the statistics registers (clear on read). It is
* important that we do this after we have tried to establish link
@@ -1116,7 +1513,8 @@ static s32 e1000_init_hw_82575(struct e1000_hw *hw)
static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
u32 phpm_reg;
DEBUGFUNC("e1000_setup_copper_link_82575");
@@ -1125,6 +1523,20 @@ static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
/* Clear Go Link Disconnect bit on supported devices */
phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
phpm_reg &= ~E1000_82580_PM_GO_LINKD;
E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
ret_val = e1000_setup_serdes_link_82575(hw);
@@ -1140,8 +1552,20 @@ static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
switch (hw->phy.type) {
case e1000_phy_i210:
case e1000_phy_m88:
ret_val = e1000_copper_link_setup_m88(hw);
switch (hw->phy.id) {
ret_val = e1000_copper_link_setup_m88_gen2(hw);
case e1000_phy_igp_3:
ret_val = e1000_copper_link_setup_igp(hw);
@@ -1173,14 +1597,16 @@ out:
static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
u32 ctrl_ext, ctrl_reg, reg;
u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
bool pcs_autoneg;
DEBUGFUNC("e1000_setup_serdes_link_82575");
* On the 82575, SerDes loopback mode persists until it is
@@ -1198,16 +1624,10 @@ static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
ctrl_reg |= E1000_CTRL_SLU;
if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
/* set both sw defined pins */
/* set both sw defined pins on 82575/82576*/
if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
/* Set switch control to serdes energy detect */
reg = E1000_READ_REG(hw, E1000_CONNSW);
reg |= E1000_CONNSW_ENRGSRC;
E1000_WRITE_REG(hw, E1000_CONNSW, reg);
reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
/* default pcs_autoneg to the same setting as mac autoneg */
@@ -1223,14 +1643,27 @@ static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
/* disable PCS autoneg and support parallel detect only */
pcs_autoneg = false;
/* fall through to default case */
if (hw->mac.type == e1000_82575 ||
hw->mac.type == e1000_82576) {
ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
DEBUGOUT("NVM Read Error\n");
if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
* non-SGMII modes only supports a speed of 1000/Full for the
* link so it is best to just force the MAC and let the pcs
* link either autoneg or be forced to 1000/Full
ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
E1000_CTRL_FD | E1000_CTRL_FRCDPX;
/* set speed of 1000/Full if speed/duplex is forced */
reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
@@ -1246,31 +1679,203 @@ static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
* However, both are supported by the hardware and some drivers/tools.
reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
* We force flow control to prevent the CTRL register values from being
* overwritten by the autonegotiated flow control values
reg |= E1000_PCS_LCTL_FORCE_FCTRL;
if (pcs_autoneg) {
/* Set PCS register for autoneg */
reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
/* Disable force flow control for autoneg */
reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
/* Configure flow control advertisement for autoneg */
anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
switch (hw->fc.requested_mode) {
case e1000_fc_full:
case e1000_fc_rx_pause:
anadv_reg |= E1000_TXCW_ASM_DIR;
anadv_reg |= E1000_TXCW_PAUSE;
case e1000_fc_tx_pause:
E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
/* Set PCS register for forced link */
reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
/* Force flow control for forced link */
DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
if (!e1000_sgmii_active_82575(hw))
if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
e1000_force_mac_fc_generic(hw);
* e1000_get_media_type_82575 - derives current media type.
* The media type is chosen reflecting few settings.
* The following are taken into account:
* - link mode set in the current port Init Control Word #3
* - current link mode settings in CSR register
* - MDIO vs. I2C PHY control interface chosen
* - SFP module media type
static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
u32 link_mode = 0;
/* Set internal phy as default */
dev_spec->module_plugged = false;
/* Get CSR setting */
/* extract link mode setting */
link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
switch (link_mode) {
case E1000_CTRL_EXT_LINK_MODE_GMII:
/* Get phy control interface type set (MDIO vs. I2C)*/
/* fall through for I2C based SGMII */
/* read media type from SFP EEPROM */
ret_val = e1000_set_sfp_media_type_82575(hw);
if ((ret_val != E1000_SUCCESS) ||
(hw->phy.media_type == e1000_media_type_unknown)) {
* If media type was not identified then return media
* type defined by the CTRL_EXT settings.
if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
/* do not change link mode for 100BaseFX */
if (dev_spec->eth_flags.e100_base_fx)
/* change current link mode setting */
ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
if (hw->phy.media_type == e1000_media_type_copper)
ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
* e1000_set_sfp_media_type_82575 - derives SFP module media type.
* The media type is chosen based on SFP module.
* compatibility flags retrieved from SFP ID EEPROM.
static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
s32 ret_val = E1000_ERR_CONFIG;
struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
u8 tranceiver_type = 0;
s32 timeout = 3;
/* Turn I2C interface ON and power on sfp cage */
ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
/* Read SFP module data */
while (timeout) {
ret_val = e1000_read_sfp_data_byte(hw,
E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
&tranceiver_type);
if (ret_val == E1000_SUCCESS)
msec_delay(100);
timeout--;
if (ret_val != E1000_SUCCESS)
E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
(u8 *)eth_flags);
/* Check if there is some SFP module plugged and powered */
if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
(tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
dev_spec->module_plugged = true;
if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
} else if (eth_flags->e100_base_fx) {
} else if (eth_flags->e1000_base_t) {
hw->phy.media_type = e1000_media_type_unknown;
DEBUGOUT("PHY module has not been recognized\n");
ret_val = E1000_SUCCESS;
out:
/* Restore I2C interface setting */
@@ -1294,7 +1899,7 @@ static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
switch(hw->phy.media_type) {
switch (hw->phy.media_type) {
case e1000_media_type_internal_serdes:
*data = ID_LED_DEFAULT_82575_SERDES;
@@ -1329,7 +1934,7 @@ static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
* Inits recommended HW defaults after a reset when there is no EEPROM
* detected. This is only for the 82575.
static s32 e1000_reset_init_script_82575(struct e1000_hw* hw)
static s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
DEBUGFUNC("e1000_reset_init_script_82575");
@@ -1385,6 +1990,28 @@ out:
* e1000_config_collision_dist_82575 - Configure collision distance
* Configures the collision distance to the default value and is used
* during link setup.
static void e1000_config_collision_dist_82575(struct e1000_hw *hw)
u32 tctl_ext;
DEBUGFUNC("e1000_config_collision_dist_82575");
tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
tctl_ext &= ~E1000_TCTL_EXT_COLD;
tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
* e1000_power_down_phy_copper_82575 - Remove link during PHY power down
@@ -1395,13 +2022,12 @@ out:
static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
if (!(phy->ops.check_reset_block))
/* If the management interface is not enabled, then power down */
if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
e1000_power_down_phy_copper(hw);
@@ -1473,7 +2099,7 @@ static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
* e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable
* e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
* After rx enable if managability is enabled then there is likely some
@@ -1491,11 +2117,11 @@ void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
/* Disable all RX queues */
/* Disable all Rx queues */
for (i = 0; i < 4; i++) {
rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
E1000_WRITE_REG(hw, E1000_RXDCTL(i),
rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
/* Poll all queues to verify they have shut down */
for (ms_wait = 0; ms_wait < 10; ms_wait++) {
@@ -1529,7 +2155,7 @@ void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
msec_delay(2);
/* Enable RX queues that were previously enabled and restore our
/* Enable Rx queues that were previously enabled and restore our
* previous state
for (i = 0; i < 4; i++)
@@ -1581,14 +2207,14 @@ static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
* 16ms to 55ms
ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
&pcie_devctl2);
pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
/* disable completion timeout resend */
gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
@@ -1597,6 +2223,45 @@ out:
* e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
* @hw: pointer to the hardware struct
* @enable: state to enter, either enabled or disabled
* @pf: Physical Function pool - do not set anti-spoofing for the PF
* enables/disables L2 switch anti-spoofing functionality.
void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
u32 reg_val, reg_offset;
reg_offset = E1000_DTXSWC;
reg_offset = E1000_TXSWC;
reg_val = E1000_READ_REG(hw, reg_offset);
if (enable) {
reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
E1000_DTXSWC_VLAN_SPOOF_MASK);
/* The PF can spoof - it has to in order to
* support emulation mode NICs
reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
E1000_WRITE_REG(hw, reg_offset, reg_val);
* e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
@@ -1606,14 +2271,32 @@ out:
void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
u32 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
u32 dtxswc;
dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
if (enable)
dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
/* Currently no other hardware supports loopback */
@@ -1646,7 +2329,6 @@ void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
u32 mdicnfg = 0;
DEBUGFUNC("e1000_read_phy_reg_82580");
@@ -1655,15 +2337,6 @@ static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
* We config the phy address in MDICNFG register now. Same bits
* as before. The values in MDIC can be written but will be
* ignored. This allows us to call the old function after
* configuring the PHY address in the new register
mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT);
E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
hw->phy.ops.release(hw);
@@ -1682,7 +2355,6 @@ out:
static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
DEBUGFUNC("e1000_write_phy_reg_82580");
@@ -1691,15 +2363,6 @@ static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
@@ -1708,6 +2371,45 @@ out:
* e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
* This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
* the values found in the EEPROM. This addresses an issue in which these
* bits are not restored from EEPROM after reset.
static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
u32 mdicnfg;
u16 nvm_data = 0;
DEBUGFUNC("e1000_reset_mdicnfg_82580");
if (hw->mac.type != e1000_82580)
ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
&nvm_data);
mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
if (nvm_data & NVM_WORD24_EXT_MDIO)
mdicnfg |= E1000_MDICNFG_EXT_MDIO;
if (nvm_data & NVM_WORD24_COM_MDIO)
mdicnfg |= E1000_MDICNFG_COM_MDIO;
* e1000_reset_hw_82580 - Reset hardware
@@ -1720,13 +2422,17 @@ static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
/* BH SW mailbox bit in SW_FW_SYNC */
u16 swmbsw_mask = E1000_SW_SYNCH_MB;
bool global_device_reset = hw->dev_spec._82575.global_device_reset;
DEBUGFUNC("e1000_reset_hw_82580");
hw->dev_spec._82575.global_device_reset = false;
/* 82580 does not reliably do global_device_reset due to hw errata */
if (hw->mac.type == e1000_82580)
global_device_reset = false;
/* Get current control state. */
ctrl = E1000_READ_REG(hw, E1000_CTRL);
@@ -1747,17 +2453,18 @@ static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
msec_delay(10);
/* Determine whether or not a global dev reset is requested */
if (global_device_reset &&
e1000_acquire_swfw_sync_82575(hw, swmbsw_mask))
if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
swmbsw_mask))
!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STAT_DEV_RST_SET))
if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
E1000_STAT_DEV_RST_SET))
ctrl |= E1000_CTRL_DEV_RST;
ctrl |= E1000_CTRL_RST;
/* Add delay to insure DEV_RST has time to complete */
if (global_device_reset)
@@ -1773,29 +2480,29 @@ static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
DEBUGOUT("Auto Read Done did not complete\n");
/* clear global device reset status bit */
E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
ret_val = e1000_reset_mdicnfg_82580(hw);
DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
/* Release semaphore */
e1000_release_swfw_sync_82575(hw, swmbsw_mask);
hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
* e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
* e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
* @data: data received by reading RXPBS register
* The 82580 uses a table based approach for packet buffer allocation sizes.
@@ -1813,3 +2520,1141 @@ u16 e1000_rxpbs_adjust_82580(u32 data)
* e1000_validate_nvm_checksum_with_offset - Validate EEPROM
* checksum
* @offset: offset in words of the checksum protected region
* Calculates the EEPROM checksum by reading/adding each word of the EEPROM
* and then verifies that the sum of the EEPROM is equal to 0xBABA.
s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
u16 checksum = 0;
u16 i, nvm_data;
DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
checksum += nvm_data;
if (checksum != (u16) NVM_SUM) {
DEBUGOUT("NVM Checksum Invalid\n");
ret_val = -E1000_ERR_NVM;
* e1000_update_nvm_checksum_with_offset - Update EEPROM
* Updates the EEPROM checksum by reading/adding each word of the EEPROM
* up to the checksum. Then calculates the EEPROM checksum and writes the
* value to the EEPROM.
s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
DEBUGOUT("NVM Read Error while updating checksum.\n");
checksum = (u16) NVM_SUM - checksum;
ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
&checksum);
DEBUGOUT("NVM Write Error while updating checksum.\n");
* e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
* Calculates the EEPROM section checksum by reading/adding each word of
* the EEPROM and then verifies that the sum of the EEPROM is
* equal to 0xBABA.
static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
u16 eeprom_regions_count = 1;
u16 j, nvm_data;
u16 nvm_offset;
DEBUGFUNC("e1000_validate_nvm_checksum_82580");
ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
/* if chekcsums compatibility bit is set validate checksums
* for all 4 ports. */
eeprom_regions_count = 4;
for (j = 0; j < eeprom_regions_count; j++) {
nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
ret_val = e1000_validate_nvm_checksum_with_offset(hw,
nvm_offset);
* e1000_update_nvm_checksum_82580 - Update EEPROM checksum
* Updates the EEPROM section checksums for all 4 ports by reading/adding
* each word of the EEPROM up to the checksum. Then calculates the EEPROM
* checksum and writes the value to the EEPROM.
static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
DEBUGFUNC("e1000_update_nvm_checksum_82580");
DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
/* set compatibility bit to validate checksums appropriately */
nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
for (j = 0; j < 4; j++) {
ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
* e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
u16 j;
DEBUGFUNC("e1000_validate_nvm_checksum_i350");
* e1000_update_nvm_checksum_i350 - Update EEPROM checksum
static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
DEBUGFUNC("e1000_update_nvm_checksum_i350");
* __e1000_access_emi_reg - Read/write EMI register
* @addr: EMI address to program
* @data: pointer to value to read/write from/to the EMI address
* @read: boolean flag to indicate read or write
static s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
u16 *data, bool read)
DEBUGFUNC("__e1000_access_emi_reg");
ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
if (read)
ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
* e1000_read_emi_reg - Read Extended Management Interface register
* @data: value to be read from the EMI address
s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
DEBUGFUNC("e1000_read_emi_reg");
return __e1000_access_emi_reg(hw, addr, data, true);
* e1000_set_eee_i350 - Enable/disable EEE support
* Enable/disable EEE based on setting in dev_spec structure.
s32 e1000_set_eee_i350(struct e1000_hw *hw)
u32 ipcnfg, eeer;
DEBUGFUNC("e1000_set_eee_i350");
if ((hw->mac.type < e1000_i350) ||
(hw->phy.media_type != e1000_media_type_copper))
ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
eeer = E1000_READ_REG(hw, E1000_EEER);
/* enable or disable per user setting */
if (!(hw->dev_spec._82575.eee_disable)) {
u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
E1000_EEER_LPI_FC);
/* This bit should not be set in normal operation. */
if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
E1000_WRITE_REG(hw, E1000_EEER, eeer);
E1000_READ_REG(hw, E1000_IPCNFG);
E1000_READ_REG(hw, E1000_EEER);
* e1000_set_eee_i354 - Enable/disable EEE support
* Enable/disable EEE legacy mode based on setting in dev_spec structure.
s32 e1000_set_eee_i354(struct e1000_hw *hw)
u16 phy_data;
DEBUGFUNC("e1000_set_eee_i354");
if ((hw->phy.media_type != e1000_media_type_copper) ||
((phy->id != M88E1543_E_PHY_ID)))
if (!hw->dev_spec._82575.eee_disable) {
/* Switch to PHY page 18. */
ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
&phy_data);
phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
phy_data);
/* Return the PHY to page 0. */
ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
/* Turn on EEE advertisement. */
ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
E1000_EEE_ADV_DEV_I354,
phy_data |= E1000_EEE_ADV_100_SUPPORTED |
E1000_EEE_ADV_1000_SUPPORTED;
ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
/* Turn off EEE advertisement. */
phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
E1000_EEE_ADV_1000_SUPPORTED);
* e1000_get_eee_status_i354 - Get EEE status
* @status: EEE status
* Get EEE status by guessing based on whether Tx or Rx LPI indications have
* been received.
s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
DEBUGFUNC("e1000_get_eee_status_i354");
/* Check if EEE is supported on this device. */
ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
E1000_PCS_STATUS_DEV_I354,
*status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
/* Due to a hw errata, if the host tries to configure the VFTA register
* while performing queries from the BMC or DMA, then the VFTA in some
* cases won't be written.
* e1000_clear_vfta_i350 - Clear VLAN filter table
* Clears the register array which contains the VLAN filter table by
* setting all the values to 0.
void e1000_clear_vfta_i350(struct e1000_hw *hw)
u32 offset;
int i;
DEBUGFUNC("e1000_clear_vfta_350");
for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
for (i = 0; i < 10; i++)
E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
* e1000_write_vfta_i350 - Write value to VLAN filter table
* @offset: register offset in VLAN filter table
* @value: register value written to VLAN filter table
* Writes value at the given offset in the register array which stores
* the VLAN filter table.
void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
DEBUGFUNC("e1000_write_vfta_350");
E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
* e1000_set_i2c_bb - Enable I2C bit-bang
* Enable I2C bit-bang interface
s32 e1000_set_i2c_bb(struct e1000_hw *hw)
u32 ctrl_ext, i2cparams;
DEBUGFUNC("e1000_set_i2c_bb");
i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
i2cparams |= E1000_I2CBB_EN;
i2cparams |= E1000_I2C_DATA_OE_N;
i2cparams |= E1000_I2C_CLK_OE_N;
E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
* e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to read
* @dev_addr: device address
* @data: value read
* Performs byte read operation over I2C interface at
* a specified device address.
s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
u8 dev_addr, u8 *data)
s32 status = E1000_SUCCESS;
u32 max_retry = 10;
u32 retry = 1;
u16 swfw_mask = 0;
bool nack = true;
DEBUGFUNC("e1000_read_i2c_byte_generic");
swfw_mask = E1000_SWFW_PHY0_SM;
do {
if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
!= E1000_SUCCESS) {
status = E1000_ERR_SWFW_SYNC;
goto read_byte_out;
e1000_i2c_start(hw);
/* Device Address and write indication */
status = e1000_clock_out_i2c_byte(hw, dev_addr);
if (status != E1000_SUCCESS)
goto fail;
status = e1000_get_i2c_ack(hw);
status = e1000_clock_out_i2c_byte(hw, byte_offset);
/* Device Address and read indication */
status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
status = e1000_clock_in_i2c_byte(hw, data);
status = e1000_clock_out_i2c_bit(hw, nack);
e1000_i2c_stop(hw);
fail:
hw->mac.ops.release_swfw_sync(hw, swfw_mask);
e1000_i2c_bus_clear(hw);
retry++;
if (retry < max_retry)
DEBUGOUT("I2C byte read error - Retrying.\n");
DEBUGOUT("I2C byte read error.\n");
} while (retry < max_retry);
read_byte_out:
return status;
* e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
* @byte_offset: byte offset to write
* @data: value to write
* Performs byte write operation over I2C interface at
s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
u8 dev_addr, u8 data)
u32 max_retry = 1;
u32 retry = 0;
DEBUGFUNC("e1000_write_i2c_byte_generic");
if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
goto write_byte_out;
status = e1000_clock_out_i2c_byte(hw, data);
DEBUGOUT("I2C byte write error - Retrying.\n");
DEBUGOUT("I2C byte write error.\n");
write_byte_out:
* e1000_i2c_start - Sets I2C start condition
* Sets I2C start condition (High -> Low on SDA while SCL is High)
static void e1000_i2c_start(struct e1000_hw *hw)
u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
DEBUGFUNC("e1000_i2c_start");
/* Start condition must begin with data and clock high */
e1000_set_i2c_data(hw, &i2cctl, 1);
e1000_raise_i2c_clk(hw, &i2cctl);
/* Setup time for start condition (4.7us) */
usec_delay(E1000_I2C_T_SU_STA);
e1000_set_i2c_data(hw, &i2cctl, 0);
/* Hold time for start condition (4us) */
usec_delay(E1000_I2C_T_HD_STA);
e1000_lower_i2c_clk(hw, &i2cctl);
/* Minimum low period of clock is 4.7 us */
usec_delay(E1000_I2C_T_LOW);
* e1000_i2c_stop - Sets I2C stop condition
* Sets I2C stop condition (Low -> High on SDA while SCL is High)
static void e1000_i2c_stop(struct e1000_hw *hw)
DEBUGFUNC("e1000_i2c_stop");
/* Stop condition must begin with data low and clock high */
/* Setup time for stop condition (4us) */
usec_delay(E1000_I2C_T_SU_STO);
/* bus free time between stop and start (4.7us)*/
usec_delay(E1000_I2C_T_BUF);
* e1000_clock_in_i2c_byte - Clocks in one byte via I2C
* @data: data byte to clock in
* Clocks in one byte data via I2C data/clock
static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
s32 i;
bool bit = 0;
DEBUGFUNC("e1000_clock_in_i2c_byte");
*data = 0;
for (i = 7; i >= 0; i--) {
e1000_clock_in_i2c_bit(hw, &bit);
*data |= bit << i;
* e1000_clock_out_i2c_byte - Clocks out one byte via I2C
* @data: data byte clocked out
* Clocks out one byte data via I2C data/clock
static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
u32 i2cctl;
DEBUGFUNC("e1000_clock_out_i2c_byte");
bit = (data >> i) & 0x1;
status = e1000_clock_out_i2c_bit(hw, bit);
/* Release SDA line (set high) */
i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
i2cctl |= E1000_I2C_DATA_OE_N;
E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
* e1000_get_i2c_ack - Polls for I2C ACK
* Clocks in/out one bit via I2C data/clock
static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
u32 i = 0;
u32 timeout = 10;
bool ack = true;
DEBUGFUNC("e1000_get_i2c_ack");
/* Minimum high period of clock is 4us */
usec_delay(E1000_I2C_T_HIGH);
/* Wait until SCL returns high */
for (i = 0; i < timeout; i++) {
usec_delay(1);
if (i2cctl & E1000_I2C_CLK_IN)
if (!(i2cctl & E1000_I2C_CLK_IN))
return E1000_ERR_I2C;
ack = e1000_get_i2c_data(&i2cctl);
if (ack) {
DEBUGOUT("I2C ack was not received.\n");
status = E1000_ERR_I2C;
* e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
* @data: read data value
* Clocks in one bit via I2C data/clock
static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
DEBUGFUNC("e1000_clock_in_i2c_bit");
*data = e1000_get_i2c_data(&i2cctl);
* e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
* @data: data value to write
* Clocks out one bit via I2C data/clock
static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
s32 status;
DEBUGFUNC("e1000_clock_out_i2c_bit");
status = e1000_set_i2c_data(hw, &i2cctl, data);
if (status == E1000_SUCCESS) {
/* Minimum low period of clock is 4.7 us.
* This also takes care of the data hold time.
DEBUGOUT1("I2C data was not set to %X\n", data);
* e1000_raise_i2c_clk - Raises the I2C SCL clock
* @i2cctl: Current value of I2CCTL register
* Raises the I2C clock line '0'->'1'
static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
DEBUGFUNC("e1000_raise_i2c_clk");
*i2cctl |= E1000_I2C_CLK_OUT;
*i2cctl &= ~E1000_I2C_CLK_OE_N;
E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
/* SCL rise time (1000ns) */
usec_delay(E1000_I2C_T_RISE);
* e1000_lower_i2c_clk - Lowers the I2C SCL clock
* Lowers the I2C clock line '1'->'0'
static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
DEBUGFUNC("e1000_lower_i2c_clk");
*i2cctl &= ~E1000_I2C_CLK_OUT;
/* SCL fall time (300ns) */
usec_delay(E1000_I2C_T_FALL);
* e1000_set_i2c_data - Sets the I2C data bit
* @data: I2C data value (0 or 1) to set
* Sets the I2C data bit
static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
DEBUGFUNC("e1000_set_i2c_data");
if (data)
*i2cctl |= E1000_I2C_DATA_OUT;
*i2cctl &= ~E1000_I2C_DATA_OUT;
*i2cctl &= ~E1000_I2C_DATA_OE_N;
*i2cctl |= E1000_I2C_CLK_OE_N;
/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
*i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
if (data != e1000_get_i2c_data(i2cctl)) {
DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
* e1000_get_i2c_data - Reads the I2C SDA data bit
* Returns the I2C data bit value
static bool e1000_get_i2c_data(u32 *i2cctl)
bool data;
DEBUGFUNC("e1000_get_i2c_data");
if (*i2cctl & E1000_I2C_DATA_IN)
data = 1;
data = 0;
return data;
* e1000_i2c_bus_clear - Clears the I2C bus
* Clears the I2C bus by sending nine clock pulses.
* Used when data line is stuck low.
void e1000_i2c_bus_clear(struct e1000_hw *hw)
u32 i;
DEBUGFUNC("e1000_i2c_bus_clear");
for (i = 0; i < 9; i++) {
/* Min high period of clock is 4us */
/* Min low period of clock is 4.7us*/
/* Put the i2c bus back to default state */
static const u8 e1000_emc_temp_data[4] = {
E1000_EMC_INTERNAL_DATA,
E1000_EMC_DIODE1_DATA,
E1000_EMC_DIODE2_DATA,
E1000_EMC_DIODE3_DATA
};
static const u8 e1000_emc_therm_limit[4] = {
E1000_EMC_INTERNAL_THERM_LIMIT,
E1000_EMC_DIODE1_THERM_LIMIT,
E1000_EMC_DIODE2_THERM_LIMIT,
E1000_EMC_DIODE3_THERM_LIMIT
* e1000_get_thermal_sensor_data_generic - Gathers thermal sensor data
* Updates the temperatures in mac.thermal_sensor_data
s32 e1000_get_thermal_sensor_data_generic(struct e1000_hw *hw)
u16 ets_offset;
u16 ets_cfg;
u16 ets_sensor;
u8 num_sensors;
u8 sensor_index;
u8 sensor_location;
u8 i;
struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
DEBUGFUNC("e1000_get_thermal_sensor_data_generic");
if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
return E1000_NOT_IMPLEMENTED;
data->sensor[0].temp = (E1000_READ_REG(hw, E1000_THMJT) & 0xFF);
/* Return the internal sensor only if ETS is unsupported */
e1000_read_nvm(hw, NVM_ETS_CFG, 1, &ets_offset);
if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
e1000_read_nvm(hw, ets_offset, 1, &ets_cfg);
if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
!= NVM_ETS_TYPE_EMC)
num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
if (num_sensors > E1000_MAX_SENSORS)
num_sensors = E1000_MAX_SENSORS;
for (i = 1; i < num_sensors; i++) {
e1000_read_nvm(hw, (ets_offset + i), 1, &ets_sensor);
sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
NVM_ETS_DATA_INDEX_SHIFT);
sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
NVM_ETS_DATA_LOC_SHIFT);
if (sensor_location != 0)
hw->phy.ops.read_i2c_byte(hw,
e1000_emc_temp_data[sensor_index],
E1000_I2C_THERMAL_SENSOR_ADDR,
&data->sensor[i].temp);
* e1000_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
* Sets the thermal sensor thresholds according to the NVM map
* and save off the threshold and location values into mac.thermal_sensor_data
s32 e1000_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
u8 low_thresh_delta;
u8 therm_limit;
DEBUGFUNC("e1000_init_thermal_sensor_thresh_generic");
memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
data->sensor[0].location = 0x1;
data->sensor[0].caution_thresh =
(E1000_READ_REG(hw, E1000_THHIGHTC) & 0xFF);
data->sensor[0].max_op_thresh =
(E1000_READ_REG(hw, E1000_THLOWTC) & 0xFF);
low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
NVM_ETS_LTHRES_DELTA_SHIFT);
for (i = 1; i <= num_sensors; i++) {
therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
hw->phy.ops.write_i2c_byte(hw,
e1000_emc_therm_limit[sensor_index],
therm_limit);
if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
data->sensor[i].location = sensor_location;
data->sensor[i].caution_thresh = therm_limit;
data->sensor[i].max_op_thresh = therm_limit -
low_thresh_delta;