↑ Collapse Diff ↑
...
 
@@ -251,13 +251,8 @@ typedef struct vmk_EthHdr {
251 251
 
typedef struct vmk_VLANHdr {
252 252
 
   /** High four bits of the VLAN ID. */
253 253
 
   vmk_uint8   vlanIDHigh:4;
254
 
   /** This field has two different interpretations. */
255
 
   union {
256
 
      /** The MAC addresses are in canonical format. */
257
 
      vmk_uint8   canonical:1;
258
 
      /** The frame is eligible to be dropped in the presence of congestion. */
259
 
      vmk_uint8   dropEligible:1;
260
 
   };
254
 
   /** The frame is eligible to be dropped in the presence of congestion. */
255
 
   vmk_uint8   dropEligible:1;
261 256
 
   /** Priority tag. */
262 257
 
   vmk_uint8   priority:3;
263 258
 
   /** Low eight bits of the VLAN ID. */
...
 
@@ -251,13 +251,8 @@ typedef struct vmk_EthHdr {
251 251
 
typedef struct vmk_VLANHdr {
252 252
 
   /** High four bits of the VLAN ID. */
253 253
 
   vmk_uint8   vlanIDHigh:4;
254
 
   /** This field has two different interpretations. */
255
 
   union {
256
 
      /** The MAC addresses are in canonical format. */
257
 
      vmk_uint8   canonical:1;
258
 
      /** The frame is eligible to be dropped in the presence of congestion. */
259
 
      vmk_uint8   dropEligible:1;
260
 
   };
254
 
   /** The frame is eligible to be dropped in the presence of congestion. */
255
 
   vmk_uint8   dropEligible:1;
261 256
 
   /** Priority tag. */
262 257
 
   vmk_uint8   priority:3;
263 258
 
   /** Low eight bits of the VLAN ID. */
1
 
#define BUILD_NUMBER "build-1604073"
2
 
#define BUILD_NUMBER_NUMERIC 1604073
3
 
#define BUILD_NUMBER_NUMERIC_STRING "1604073"
4
 
#define PRODUCT_BUILD_NUMBER "product-build-4509"
5
 
#define PRODUCT_BUILD_NUMBER_NUMERIC 4509
6
 
#define PRODUCT_BUILD_NUMBER_NUMERIC_STRING "4509"
1
 
#define BUILD_NUMBER "build-1623387"
2
 
#define BUILD_NUMBER_NUMERIC 1623387
3
 
#define BUILD_NUMBER_NUMERIC_STRING "1623387"
4
 
#define PRODUCT_BUILD_NUMBER "product-build-4950"
5
 
#define PRODUCT_BUILD_NUMBER_NUMERIC 4950
6
 
#define PRODUCT_BUILD_NUMBER_NUMERIC_STRING "4950"
1 1
 
The following assumes the files disclosed for this package have been
2
 
copied to the directory "/usr/vmware/src", and any commands that need to
3
 
be executed for the disclosure should be executed from this directory
4
 
on a "centos-5.3-x64" system (see the file "SYSTEMS.txt" for definition
5
 
of this system).
2
 
copied to the directory "/usr/vmware/src":
3
 

	
4
 
rm -rf /usr/vmware/src
5
 
mkdir /usr/vmware/src
6
 
cp * /usr/vmware/src 
7
 

	
8
 
And any commands that need to be executed for the disclosure should be
9
 
executed from this directory on a "centos-5.3-x64" system (see the file
10
 
"SYSTEMS.txt" for definition of this system).
6 11
 

	
7 12
 
This package should be built on a "centos-5.3-x64" system.  Please see the
8 13
 
"System Configurations" document for a definition of the configuration
 
new file 100644
1
 
<verify>
2
 
    <virtual-infrastructure>
3
 
        <address>10.111.110.45</address>
4
 
        <username>root</username>
5
 
        <password>password</password>
6
 
        <vm type="build">
7
 
            <id>centos-5.3-x64</id>
8
 
            <realname>Rush-CentOS-5.3-x64</realname>
9
 
            <os>linux</os>
10
 
            <username>root</username>
11
 
            <password>welcome</password>
12
 
        </vm>
13
 
    </virtual-infrastructure>
14
 
    <virtual-infrastructure>
15
 
        <address>10.111.110.98</address>
16
 
        <username>root</username>
17
 
        <password>welcome</password>
18
 
        <vm type="install">
19
 
            <id>BDE-Management-Server</id>
20
 
            <realname>management-server</realname>
21
 
            <os>linux</os>
22
 
            <username>root</username>
23
 
            <password>vmware</password>
24
 
        </vm>
25
 
    </virtual-infrastructure>
26
 
</verify>
 
new file 100644
1
 
<?xml version="1.0" encoding="UTF-8"?>
2
 
<disclosure>
3
 
    <name>vmkdrivers</name>
4
 
    <version>gpl</version>
5
 
    <category>VMWsource</category>
6
 
    <build>
7
 
		<target>centos-5.3-x64</target>
8
 
        <files>
9
 
            <file>vmkdrivers-gpl.tgz</file>
10
 
            <file>collect-drivers.sh</file>
11
 
            <file>update-drivers.sh</file>
12
 
        </files>
13
 
        <process>
14
 
            <execute>tar xzf vmkdrivers-gpl.tgz</execute>
15
 
            <execute>sh ./build-vmkdrivers.sh</execute>
16
 
            <execute>mv collect-drivers.sh BLD/build/collect-drivers.sh</execute>
17
 
            <execute>cd BLD/build</execute>
18
 
            <execute>./collect-drivers.sh</execute>
19
 
        </process>
20
 
        <deliveries>
21
 
            <delivery dir="BLD/build">drivers</delivery>
22
 
            <delivery>update-drivers.sh</delivery>
23
 
        </deliveries>
24
 
        <output>centos-5.3-x64</output>
25
 
    </build>
26
 
</disclosure>
1 1
 
/*
2
 
 * Portions Copyright 2008 - 2010 VMware, Inc.
2
 
 * Portions Copyright 2008 - 2013 VMware, Inc.
3 3
 
 */
4 4
 
/*
5 5
 
 *  ahci.c - AHCI SATA support
...
 
@@ -54,7 +54,7 @@
54 54
 
#endif
55 55
 

	
56 56
 
#define DRV_NAME	"ahci"
57
 
#define DRV_VERSION	"3.0-17vmw"
57
 
#define DRV_VERSION	"3.0-18vmw"
58 58
 

	
59 59
 
#if defined(__VMKLNX__)
60 60
 
static int ahci_skip_host_reset = 0;
...
 
@@ -634,6 +634,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
634 634
 
        { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
635 635
 
        { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
636 636
 
        { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
637
 
        { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
638
 
        { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Wellsburg RAID */
639
 
        { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
637 640
 
        { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
638 641
 
        { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
639 642
 
        { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
...
 
@@ -1968,7 +1971,6 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1968 1971
 
	if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1969 1972
 
#if defined(__VMKLNX__)
1970 1973
 
		if ((irq_stat & PORT_IRQ_PHYRDY) && (ap->link.device[0].sdev)) {
1971
 
			vmklnx_scsi_device_hot_removed(ap->link.device[0].sdev);
1972 1974
 
			ata_ehi_push_desc(host_ehi, "hotplug handled");
1973 1975
 
		}
1974 1976
 
#endif
...
 
@@ -91,7 +91,7 @@
91 91
 
#include "bnx2_fw2.h"
92 92
 

	
93 93
 
#define DRV_MODULE_NAME		"bnx2"
94
 
#define DRV_MODULE_VERSION     "2.2.3h.v55.2"
94
 
#define DRV_MODULE_VERSION     "2.2.3d.v55.2"
95 95
 
#define DRV_MODULE_RELDATE     "Feb 12, 2013"
96 96
 
#define RUN_AT(x) (jiffies + (x))
97 97
 

	
...
 
@@ -15,7 +15,7 @@
15 15
 
#ifndef CNIC_REGISTER_H
16 16
 
#define CNIC_REGISTER_H
17 17
 

	
18
 
#define CNIC_REGISTER_MODULE_VERSION	"1.72.2.v55.1"
18
 
#define CNIC_REGISTER_MODULE_VERSION	"1.72.1.v50.1i"
19 19
 
#define CNIC_REGISTER_MODULE_RELDATE	"February 06, 2013"
20 20
 
extern int cnic_register_adapter(const char * name, void *callback);
21 21
 
extern void *cnic_register_get_callback(const char * name);
...
 
@@ -15,7 +15,7 @@
15 15
 
#ifndef CNIC_REGISTER_H
16 16
 
#define CNIC_REGISTER_H
17 17
 

	
18
 
#define CNIC_REGISTER_MODULE_VERSION	"1.72.2.v55.1"
18
 
#define CNIC_REGISTER_MODULE_VERSION	"1.72.1.v50.1i"
19 19
 
#define CNIC_REGISTER_MODULE_RELDATE	"February 06, 2013"
20 20
 
extern int cnic_register_adapter(const char * name, void *callback);
21 21
 
extern void *cnic_register_get_callback(const char * name);
...
 
@@ -997,6 +997,14 @@ static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
997 997
 
		reg |= (1 << 28);
998 998
 
	ew32(TARC(1), reg);
999 999
 

	
1000
 
	/*
1001
 
	 * Disable IPv6 extension header parsing because some malformed
1002
 
	 * IPv6 headers can hang the Rx.
1003
 
	 */
1004
 
	reg = er32(RFCTL);
1005
 
	reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1006
 
	ew32(RFCTL, reg);
1007
 

	
1000 1008
 
	return;
1001 1009
 
}
1002 1010
 

	
...
 
@@ -1184,6 +1184,16 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1184 1184
 
		ew32(CTRL_EXT, reg);
1185 1185
 
	}
1186 1186
 

	
1187
 
	/*
1188
 
	 * Disable IPv6 extension header parsing because some malformed
1189
 
	 * IPv6 headers can hang the Rx.
1190
 
	 */
1191
 
	if (hw->mac.type <= e1000_82573) {
1192
 
		reg = er32(RFCTL);
1193
 
		reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1194
 
		ew32(RFCTL, reg);
1195
 
	}
1196
 

	
1187 1197
 
	/* PCI-Ex Control Registers */
1188 1198
 

	
1189 1199
 
	switch (hw->mac.type) {
...
 
@@ -2785,6 +2785,21 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2785 2785
 
		ew32(STATUS, reg);
2786 2786
 
	}
2787 2787
 

	
2788
 
	/*
2789
 
	 * work-around descriptor data corruption issue during nfs v2 udp
2790
 
	 * traffic,just disable the nfs filtering capability
2791
 
	 */
2792
 
	reg = er32(RFCTL);
2793
 
	reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
2794
 

	
2795
 
	/*
2796
 
	 * Disable IPv6 extension header parsing because some
2797
 
	 * malformed IPv6 headers can hang the Rx.
2798
 
	 */
2799
 
	if (hw->mac.type == e1000_ich8lan)
2800
 
		reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
2801
 
	ew32(RFCTL, reg);
2802
 

	
2788 2803
 
	return;
2789 2804
 
}
2790 2805
 

	
1 1
 
/*******************************************************************************
2 2
 

	
3 3
 
  Intel(R) Gigabit Ethernet Linux driver
4
 
  Copyright(c) 2007-2009 Intel Corporation.
4
 
  Copyright(c) 2007-2013 Intel Corporation.
5 5
 

	
6 6
 
  This program is free software; you can redistribute it and/or modify it
7 7
 
  under the terms and conditions of the GNU General Public License,
...
 
@@ -31,57 +31,125 @@
31 31
 
 * 82575GB Gigabit Network Connection
32 32
 
 * 82576 Gigabit Network Connection
33 33
 
 * 82576 Quad Port Gigabit Mezzanine Adapter
34
 
 * 82580 Gigabit Network Connection
35
 
 * I350 Gigabit Network Connection
34 36
 
 */
35 37
 

	
36 38
 
#include "e1000_api.h"
39
 
#include "e1000_i210.h"
37 40
 

	
38 41
 
static s32  e1000_init_phy_params_82575(struct e1000_hw *hw);
39
 
static s32  e1000_init_nvm_params_82575(struct e1000_hw *hw);
40 42
 
static s32  e1000_init_mac_params_82575(struct e1000_hw *hw);
41 43
 
static s32  e1000_acquire_phy_82575(struct e1000_hw *hw);
42 44
 
static void e1000_release_phy_82575(struct e1000_hw *hw);
43 45
 
static s32  e1000_acquire_nvm_82575(struct e1000_hw *hw);
44 46
 
static void e1000_release_nvm_82575(struct e1000_hw *hw);
45 47
 
static s32  e1000_check_for_link_82575(struct e1000_hw *hw);
48
 
static s32  e1000_check_for_link_media_swap(struct e1000_hw *hw);
46 49
 
static s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
47 50
 
static s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
48
 
                                         u16 *duplex);
51
 
					 u16 *duplex);
49 52
 
static s32  e1000_init_hw_82575(struct e1000_hw *hw);
50 53
 
static s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
51 54
 
static s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
52
 
                                           u16 *data);
55
 
					   u16 *data);
53 56
 
static s32  e1000_reset_hw_82575(struct e1000_hw *hw);
54 57
 
static s32  e1000_reset_hw_82580(struct e1000_hw *hw);
55
 
static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
56
 
                                    u32 offset, u16 *data);
57
 
static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
58
 
                                     u32 offset, u16 data);
58
 
static s32  e1000_read_phy_reg_82580(struct e1000_hw *hw,
59
 
				     u32 offset, u16 *data);
60
 
static s32  e1000_write_phy_reg_82580(struct e1000_hw *hw,
61
 
				      u32 offset, u16 data);
62
 
static s32  e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
63
 
					  bool active);
64
 
static s32  e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
65
 
					  bool active);
59 66
 
static s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
60
 
                                          bool active);
67
 
					  bool active);
61 68
 
static s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
62 69
 
static s32  e1000_setup_serdes_link_82575(struct e1000_hw *hw);
70
 
static s32  e1000_get_media_type_82575(struct e1000_hw *hw);
71
 
static s32  e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
63 72
 
static s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
64 73
 
static s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
65
 
                                            u32 offset, u16 data);
74
 
					    u32 offset, u16 data);
66 75
 
static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
67 76
 
static s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
68 77
 
static s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
69
 
                                                 u16 *speed, u16 *duplex);
78
 
						 u16 *speed, u16 *duplex);
70 79
 
static s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
71 80
 
static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
72 81
 
static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
73 82
 
static s32  e1000_reset_init_script_82575(struct e1000_hw *hw);
74 83
 
static s32  e1000_read_mac_addr_82575(struct e1000_hw *hw);
84
 
static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
75 85
 
static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
76 86
 
static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
87
 
static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
77 88
 
static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
78
 

	
79
 
static const u16 e1000_82580_rxpbs_table[] =
80
 
	{ 36, 72, 144, 1, 2, 4, 8, 16,
81
 
	  35, 70, 140 };
89
 
static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
90
 
static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
91
 
static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
92
 
static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
93
 
						 u16 offset);
94
 
static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
95
 
						   u16 offset);
96
 
static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
97
 
static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
98
 
static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
99
 
static void e1000_clear_vfta_i350(struct e1000_hw *hw);
100
 

	
101
 
static void e1000_i2c_start(struct e1000_hw *hw);
102
 
static void e1000_i2c_stop(struct e1000_hw *hw);
103
 
static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
104
 
static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
105
 
static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
106
 
static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
107
 
static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
108
 
static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
109
 
static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
110
 
static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
111
 
static bool e1000_get_i2c_data(u32 *i2cctl);
112
 

	
113
 
static const u16 e1000_82580_rxpbs_table[] = {
114
 
	36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
82 115
 
#define E1000_82580_RXPBS_TABLE_SIZE \
83 116
 
	(sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
84 117
 

	
118
 

	
119
 
/**
120
 
 *  e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
121
 
 *  @hw: pointer to the HW structure
122
 
 *
123
 
 *  Called to determine if the I2C pins are being used for I2C or as an
124
 
 *  external MDIO interface since the two options are mutually exclusive.
125
 
 **/
126
 
static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
127
 
{
128
 
	u32 reg = 0;
129
 
	bool ext_mdio = false;
130
 

	
131
 
	DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
132
 

	
133
 
	switch (hw->mac.type) {
134
 
	case e1000_82575:
135
 
	case e1000_82576:
136
 
		reg = E1000_READ_REG(hw, E1000_MDIC);
137
 
		ext_mdio = !!(reg & E1000_MDIC_DEST);
138
 
		break;
139
 
	case e1000_82580:
140
 
	case e1000_i350:
141
 
	case e1000_i354:
142
 
	case e1000_i210:
143
 
	case e1000_i211:
144
 
		reg = E1000_READ_REG(hw, E1000_MDICNFG);
145
 
		ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
146
 
		break;
147
 
	default:
148
 
		break;
149
 
	}
150
 
	return ext_mdio;
151
 
}
152
 

	
85 153
 
/**
86 154
 
 *  e1000_init_phy_params_82575 - Init PHY func ptrs.
87 155
 
 *  @hw: pointer to the HW structure
...
 
@@ -90,9 +158,13 @@ static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
90 158
 
{
91 159
 
	struct e1000_phy_info *phy = &hw->phy;
92 160
 
	s32 ret_val = E1000_SUCCESS;
161
 
	u32 ctrl_ext;
93 162
 

	
94 163
 
	DEBUGFUNC("e1000_init_phy_params_82575");
95 164
 

	
165
 
	phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
166
 
	phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
167
 

	
96 168
 
	if (hw->phy.media_type != e1000_media_type_copper) {
97 169
 
		phy->type = e1000_phy_none;
98 170
 
		goto out;
...
 
@@ -101,27 +173,48 @@ static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
101 173
 
	phy->ops.power_up   = e1000_power_up_phy_copper;
102 174
 
	phy->ops.power_down = e1000_power_down_phy_copper_82575;
103 175
 

	
104
 
	phy->autoneg_mask           = AUTONEG_ADVERTISE_SPEED_DEFAULT;
105
 
	phy->reset_delay_us         = 100;
176
 
	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
177
 
	phy->reset_delay_us	= 100;
106 178
 

	
107
 
	phy->ops.acquire            = e1000_acquire_phy_82575;
108
 
	phy->ops.check_reset_block  = e1000_check_reset_block_generic;
109
 
	phy->ops.commit             = e1000_phy_sw_reset_generic;
110
 
	phy->ops.get_cfg_done       = e1000_get_cfg_done_82575;
111
 
	phy->ops.release            = e1000_release_phy_82575;
179
 
	phy->ops.acquire	= e1000_acquire_phy_82575;
180
 
	phy->ops.check_reset_block = e1000_check_reset_block_generic;
181
 
	phy->ops.commit		= e1000_phy_sw_reset_generic;
182
 
	phy->ops.get_cfg_done	= e1000_get_cfg_done_82575;
183
 
	phy->ops.release	= e1000_release_phy_82575;
184
 

	
185
 
	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
112 186
 

	
113 187
 
	if (e1000_sgmii_active_82575(hw)) {
114
 
		phy->ops.reset      = e1000_phy_hw_reset_sgmii_82575;
115
 
		phy->ops.read_reg   = e1000_read_phy_reg_sgmii_82575;
116
 
		phy->ops.write_reg  = e1000_write_phy_reg_sgmii_82575;
117
 
	} else if (hw->mac.type >= e1000_82580) {
118
 
		phy->ops.reset      = e1000_phy_hw_reset_generic;
119
 
		phy->ops.read_reg   = e1000_read_phy_reg_82580;
120
 
		phy->ops.write_reg  = e1000_write_phy_reg_82580;
188
 
		phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
189
 
		ctrl_ext |= E1000_CTRL_I2C_ENA;
190
 
	} else {
191
 
		phy->ops.reset = e1000_phy_hw_reset_generic;
192
 
		ctrl_ext &= ~E1000_CTRL_I2C_ENA;
193
 
	}
194
 

	
195
 
	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
196
 
	e1000_reset_mdicnfg_82580(hw);
197
 

	
198
 
	if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
199
 
		phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
200
 
		phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
121 201
 
	} else {
122
 
		phy->ops.reset      = e1000_phy_hw_reset_generic;
123
 
		phy->ops.read_reg   = e1000_read_phy_reg_igp;
124
 
		phy->ops.write_reg  = e1000_write_phy_reg_igp;
202
 
		switch (hw->mac.type) {
203
 
		case e1000_82580:
204
 
		case e1000_i350:
205
 
		case e1000_i354:
206
 
			phy->ops.read_reg = e1000_read_phy_reg_82580;
207
 
			phy->ops.write_reg = e1000_write_phy_reg_82580;
208
 
			break;
209
 
		case e1000_i210:
210
 
		case e1000_i211:
211
 
			phy->ops.read_reg = e1000_read_phy_reg_gs40g;
212
 
			phy->ops.write_reg = e1000_write_phy_reg_gs40g;
213
 
			break;
214
 
		default:
215
 
			phy->ops.read_reg = e1000_read_phy_reg_igp;
216
 
			phy->ops.write_reg = e1000_write_phy_reg_igp;
217
 
		}
125 218
 
	}
126 219
 

	
127 220
 
	/* Set phy->phy_addr and phy->id. */
...
 
@@ -129,30 +222,78 @@ static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
129 222
 

	
130 223
 
	/* Verify phy id and set remaining function pointers */
131 224
 
	switch (phy->id) {
225
 
	case M88E1543_E_PHY_ID:
226
 
	case I347AT4_E_PHY_ID:
227
 
	case M88E1112_E_PHY_ID:
228
 
	case M88E1340M_E_PHY_ID:
132 229
 
	case M88E1111_I_PHY_ID:
133
 
		phy->type                   = e1000_phy_m88;
134
 
		phy->ops.check_polarity     = e1000_check_polarity_m88;
135
 
		phy->ops.get_info           = e1000_get_phy_info_m88;
136
 
		phy->ops.get_cable_length   = e1000_get_cable_length_m88;
230
 
		phy->type		= e1000_phy_m88;
231
 
		phy->ops.check_polarity	= e1000_check_polarity_m88;
232
 
		phy->ops.get_info	= e1000_get_phy_info_m88;
233
 
		if (phy->id == I347AT4_E_PHY_ID ||
234
 
		    phy->id == M88E1112_E_PHY_ID ||
235
 
		    phy->id == M88E1340M_E_PHY_ID)
236
 
			phy->ops.get_cable_length =
237
 
					 e1000_get_cable_length_m88_gen2;
238
 
		else if (phy->id == M88E1543_E_PHY_ID)
239
 
			phy->ops.get_cable_length =
240
 
					 e1000_get_cable_length_m88_gen2;
241
 
		else
242
 
			phy->ops.get_cable_length = e1000_get_cable_length_m88;
137 243
 
		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
244
 
		/* Check if this PHY is confgured for media swap. */
245
 
		if (phy->id == M88E1112_E_PHY_ID) {
246
 
			u16 data;
247
 

	
248
 
			ret_val = phy->ops.write_reg(hw,
249
 
						     E1000_M88E1112_PAGE_ADDR,
250
 
						     2);
251
 
			if (ret_val)
252
 
				goto out;
253
 

	
254
 
			ret_val = phy->ops.read_reg(hw,
255
 
						    E1000_M88E1112_MAC_CTRL_1,
256
 
						    &data);
257
 
			if (ret_val)
258
 
				goto out;
259
 

	
260
 
			data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
261
 
			       E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
262
 
			if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
263
 
			    data == E1000_M88E1112_AUTO_COPPER_BASEX)
264
 
				hw->mac.ops.check_for_link =
265
 
						e1000_check_for_link_media_swap;
266
 
		}
138 267
 
		break;
139 268
 
	case IGP03E1000_E_PHY_ID:
140 269
 
	case IGP04E1000_E_PHY_ID:
141
 
		phy->type                   = e1000_phy_igp_3;
142
 
		phy->ops.check_polarity     = e1000_check_polarity_igp;
143
 
		phy->ops.get_info           = e1000_get_phy_info_igp;
144
 
		phy->ops.get_cable_length   = e1000_get_cable_length_igp_2;
270
 
		phy->type = e1000_phy_igp_3;
271
 
		phy->ops.check_polarity = e1000_check_polarity_igp;
272
 
		phy->ops.get_info = e1000_get_phy_info_igp;
273
 
		phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
145 274
 
		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
146
 
		phy->ops.set_d0_lplu_state  = e1000_set_d0_lplu_state_82575;
147
 
		phy->ops.set_d3_lplu_state  = e1000_set_d3_lplu_state_generic;
275
 
		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
276
 
		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
148 277
 
		break;
149 278
 
	case I82580_I_PHY_ID:
150 279
 
	case I350_I_PHY_ID:
151
 
		phy->type                   = e1000_phy_82580;
152
 
		phy->ops.check_polarity     = e1000_check_polarity_82577;
153
 
		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82577;
154
 
		phy->ops.get_cable_length   = e1000_get_cable_length_82577;
155
 
		phy->ops.get_info           = e1000_get_phy_info_82577;
280
 
		phy->type = e1000_phy_82580;
281
 
		phy->ops.check_polarity = e1000_check_polarity_82577;
282
 
		phy->ops.force_speed_duplex =
283
 
					 e1000_phy_force_speed_duplex_82577;
284
 
		phy->ops.get_cable_length = e1000_get_cable_length_82577;
285
 
		phy->ops.get_info = e1000_get_phy_info_82577;
286
 
		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
287
 
		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
288
 
		break;
289
 
	case I210_I_PHY_ID:
290
 
		phy->type		= e1000_phy_i210;
291
 
		phy->ops.check_polarity	= e1000_check_polarity_m88;
292
 
		phy->ops.get_info	= e1000_get_phy_info_m88;
293
 
		phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
294
 
		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
295
 
		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
296
 
		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
156 297
 
		break;
157 298
 
	default:
158 299
 
		ret_val = -E1000_ERR_PHY;
...
 
@@ -167,7 +308,7 @@ out:
167 308
 
 *  e1000_init_nvm_params_82575 - Init NVM func ptrs.
168 309
 
 *  @hw: pointer to the HW structure
169 310
 
 **/
170
 
static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
311
 
s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
171 312
 
{
172 313
 
	struct e1000_nvm_info *nvm = &hw->nvm;
173 314
 
	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
...
 
@@ -175,47 +316,75 @@ static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
175 316
 

	
176 317
 
	DEBUGFUNC("e1000_init_nvm_params_82575");
177 318
 

	
178
 
	nvm->opcode_bits        = 8;
179
 
	nvm->delay_usec         = 1;
180
 
	switch (nvm->override) {
181
 
	case e1000_nvm_override_spi_large:
182
 
		nvm->page_size    = 32;
183
 
		nvm->address_bits = 16;
184
 
		break;
185
 
	case e1000_nvm_override_spi_small:
186
 
		nvm->page_size    = 8;
187
 
		nvm->address_bits = 8;
188
 
		break;
189
 
	default:
190
 
		nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
191
 
		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
192
 
		break;
193
 
	}
194
 

	
195
 
	nvm->type              = e1000_nvm_eeprom_spi;
196
 

	
197 319
 
	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
198
 
	                  E1000_EECD_SIZE_EX_SHIFT);
199
 

	
320
 
		     E1000_EECD_SIZE_EX_SHIFT);
200 321
 
	/*
201 322
 
	 * Added to a constant, "size" becomes the left-shift value
202 323
 
	 * for setting word_size.
203 324
 
	 */
204 325
 
	size += NVM_WORD_SIZE_BASE_SHIFT;
205 326
 

	
206
 
	/* EEPROM access above 16k is unsupported */
207
 
	if (size > 14)
208
 
		size = 14;
327
 
	/* Just in case size is out of range, cap it to the largest
328
 
	 * EEPROM size supported
329
 
	 */
330
 
	if (size > 15)
331
 
		size = 15;
332
 

	
209 333
 
	nvm->word_size = 1 << size;
334
 
	if (hw->mac.type < e1000_i210) {
335
 
		nvm->opcode_bits = 8;
336
 
		nvm->delay_usec = 1;
337
 

	
338
 
		switch (nvm->override) {
339
 
		case e1000_nvm_override_spi_large:
340
 
			nvm->page_size = 32;
341
 
			nvm->address_bits = 16;
342
 
			break;
343
 
		case e1000_nvm_override_spi_small:
344
 
			nvm->page_size = 8;
345
 
			nvm->address_bits = 8;
346
 
			break;
347
 
		default:
348
 
			nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
349
 
			nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
350
 
					    16 : 8;
351
 
			break;
352
 
		}
353
 
		if (nvm->word_size == (1 << 15))
354
 
			nvm->page_size = 128;
355
 

	
356
 
		nvm->type = e1000_nvm_eeprom_spi;
357
 
	} else {
358
 
		nvm->type = e1000_nvm_flash_hw;
359
 
	}
210 360
 

	
211 361
 
	/* Function Pointers */
212
 
	nvm->ops.acquire       = e1000_acquire_nvm_82575;
213
 
	nvm->ops.read          = e1000_read_nvm_eerd;
214
 
	nvm->ops.release       = e1000_release_nvm_82575;
215
 
	nvm->ops.update        = e1000_update_nvm_checksum_generic;
362
 
	nvm->ops.acquire = e1000_acquire_nvm_82575;
363
 
	nvm->ops.release = e1000_release_nvm_82575;
364
 
	if (nvm->word_size < (1 << 15))
365
 
		nvm->ops.read = e1000_read_nvm_eerd;
366
 
	else
367
 
		nvm->ops.read = e1000_read_nvm_spi;
368
 

	
369
 
	nvm->ops.write = e1000_write_nvm_spi;
370
 
	nvm->ops.validate = e1000_validate_nvm_checksum_generic;
371
 
	nvm->ops.update = e1000_update_nvm_checksum_generic;
216 372
 
	nvm->ops.valid_led_default = e1000_valid_led_default_82575;
217
 
	nvm->ops.validate      = e1000_validate_nvm_checksum_generic;
218
 
	nvm->ops.write         = e1000_write_nvm_spi;
373
 

	
374
 
	/* override generic family function pointers for specific descendants */
375
 
	switch (hw->mac.type) {
376
 
	case e1000_82580:
377
 
		nvm->ops.validate = e1000_validate_nvm_checksum_82580;
378
 
		nvm->ops.update = e1000_update_nvm_checksum_82580;
379
 
		break;
380
 
	case e1000_i350:
381
 
	case e1000_i354:
382
 
		nvm->ops.validate = e1000_validate_nvm_checksum_i350;
383
 
		nvm->ops.update = e1000_update_nvm_checksum_i350;
384
 
		break;
385
 
	default:
386
 
		break;
387
 
	}
219 388
 

	
220 389
 
	return E1000_SUCCESS;
221 390
 
}
...
 
@@ -228,46 +397,11 @@ static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
228 397
 
{
229 398
 
	struct e1000_mac_info *mac = &hw->mac;
230 399
 
	struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
231
 
	u32 ctrl_ext = 0;
232 400
 

	
233 401
 
	DEBUGFUNC("e1000_init_mac_params_82575");
234 402
 

	
235
 
	/* Set media type */
236
 
        /*
237
 
	 * The 82575 uses bits 22:23 for link mode. The mode can be changed
238
 
         * based on the EEPROM. We cannot rely upon device ID. There
239
 
         * is no distinguishable difference between fiber and internal
240
 
         * SerDes mode on the 82575. There can be an external PHY attached
241
 
         * on the SGMII interface. For this, we'll set sgmii_active to true.
242
 
         */
243
 
	hw->phy.media_type = e1000_media_type_copper;
244
 
	dev_spec->sgmii_active = false;
245
 

	
246
 
	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
247
 
	switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
248
 
	case E1000_CTRL_EXT_LINK_MODE_SGMII:
249
 
		dev_spec->sgmii_active = true;
250
 
		ctrl_ext |= E1000_CTRL_I2C_ENA;
251
 
		break;
252
 
	case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
253
 
	case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
254
 
		hw->phy.media_type = e1000_media_type_internal_serdes;
255
 
		ctrl_ext |= E1000_CTRL_I2C_ENA;
256
 
		break;
257
 
	default:
258
 
		ctrl_ext &= ~E1000_CTRL_I2C_ENA;
259
 
		break;
260
 
	}
261
 

	
262
 
	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
263
 

	
264
 
	/*
265
 
	 * if using i2c make certain the MDICNFG register is cleared to prevent
266
 
	 * communications from being misrouted to the mdic registers
267
 
	 */
268
 
	if ((ctrl_ext & E1000_CTRL_I2C_ENA) && (hw->mac.type == e1000_82580))
269
 
		E1000_WRITE_REG(hw, E1000_MDICNFG, 0);
270
 

	
403
 
	/* Derives media type */
404
 
	e1000_get_media_type_82575(hw);
271 405
 
	/* Set mta register count */
272 406
 
	mac->mta_reg_count = 128;
273 407
 
	/* Set uta register count */
...
 
@@ -278,21 +412,31 @@ static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
278 412
 
		mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
279 413
 
	if (mac->type == e1000_82580)
280 414
 
		mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
281
 
	if (mac->type == e1000_i350)
415
 
	if (mac->type == e1000_i350 || mac->type == e1000_i354)
282 416
 
		mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
417
 

	
418
 
	/* Enable EEE default settings for EEE supported devices */
419
 
	if (mac->type >= e1000_i350)
420
 
		dev_spec->eee_disable = false;
421
 

	
422
 
	/* Allow a single clear of the SW semaphore on I210 and newer */
423
 
	if (mac->type >= e1000_i210)
424
 
		dev_spec->clear_semaphore_once = true;
425
 

	
283 426
 
	/* Set if part includes ASF firmware */
284 427
 
	mac->asf_firmware_present = true;
285
 
	/* Set if manageability features are enabled. */
428
 
	/* FWSM register */
429
 
	mac->has_fwsm = true;
430
 
	/* ARC supported; valid only if manageability features are enabled. */
286 431
 
	mac->arc_subsystem_valid =
287
 
	        (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
288
 
	                ? true : false;
432
 
		!!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
289 433
 

	
290 434
 
	/* Function pointers */
291 435
 

	
292 436
 
	/* bus type/speed/width */
293 437
 
	mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
294 438
 
	/* reset */
295
 
	if (mac->type == e1000_82580)
439
 
	if (mac->type >= e1000_82580)
296 440
 
		mac->ops.reset_hw = e1000_reset_hw_82580;
297 441
 
	else
298 442
 
	mac->ops.reset_hw = e1000_reset_hw_82575;
...
 
@@ -302,25 +446,34 @@ static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
302 446
 
	mac->ops.setup_link = e1000_setup_link_generic;
303 447
 
	/* physical interface link setup */
304 448
 
	mac->ops.setup_physical_interface =
305
 
	        (hw->phy.media_type == e1000_media_type_copper)
306
 
	                ? e1000_setup_copper_link_82575
307
 
	                : e1000_setup_serdes_link_82575;
449
 
		(hw->phy.media_type == e1000_media_type_copper)
450
 
		? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
308 451
 
	/* physical interface shutdown */
309 452
 
	mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
453
 
	/* physical interface power up */
454
 
	mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
310 455
 
	/* check for link */
311 456
 
	mac->ops.check_for_link = e1000_check_for_link_82575;
312
 
	/* receive address register setting */
313
 
	mac->ops.rar_set = e1000_rar_set_generic;
314 457
 
	/* read mac address */
315 458
 
	mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
459
 
	/* configure collision distance */
460
 
	mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
316 461
 
	/* multicast address update */
317 462
 
	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
318
 
	/* writing VFTA */
319
 
	mac->ops.write_vfta = e1000_write_vfta_generic;
320
 
	/* clearing VFTA */
321
 
	mac->ops.clear_vfta = e1000_clear_vfta_generic;
322
 
	/* setting MTA */
323
 
	mac->ops.mta_set = e1000_mta_set_generic;
463
 
	if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
464
 
		/* writing VFTA */
465
 
		mac->ops.write_vfta = e1000_write_vfta_i350;
466
 
		/* clearing VFTA */
467
 
		mac->ops.clear_vfta = e1000_clear_vfta_i350;
468
 
	} else {
469
 
		/* writing VFTA */
470
 
		mac->ops.write_vfta = e1000_write_vfta_generic;
471
 
		/* clearing VFTA */
472
 
		mac->ops.clear_vfta = e1000_clear_vfta_generic;
473
 
	}
474
 
	if (hw->mac.type >= e1000_82580)
475
 
		mac->ops.validate_mdi_setting =
476
 
				e1000_validate_mdi_setting_crossover_generic;
324 477
 
	/* ID LED init */
325 478
 
	mac->ops.id_led_init = e1000_id_led_init_generic;
326 479
 
	/* blink LED */
...
 
@@ -336,6 +489,18 @@ static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
336 489
 
	mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
337 490
 
	/* link info */
338 491
 
	mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
492
 
	/* get thermal sensor data */
493
 
	mac->ops.get_thermal_sensor_data =
494
 
				e1000_get_thermal_sensor_data_generic;
495
 
	mac->ops.init_thermal_sensor_thresh =
496
 
				e1000_init_thermal_sensor_thresh_generic;
497
 
	/* acquire SW_FW sync */
498
 
	mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
499
 
	mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
500
 
	if (mac->type >= e1000_i210) {
501
 
		mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
502
 
		mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
503
 
	}
339 504
 

	
340 505
 
	/* set lan id for port to determine which phy lock to use */
341 506
 
	hw->mac.ops.set_lan_id(hw);
...
 
@@ -378,7 +543,7 @@ static s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
378 543
 
	else if (hw->bus.func == E1000_FUNC_3)
379 544
 
		mask = E1000_SWFW_PHY3_SM;
380 545
 

	
381
 
	return e1000_acquire_swfw_sync_82575(hw, mask);
546
 
	return hw->mac.ops.acquire_swfw_sync(hw, mask);
382 547
 
}
383 548
 

	
384 549
 
/**
...
 
@@ -400,7 +565,7 @@ static void e1000_release_phy_82575(struct e1000_hw *hw)
400 565
 
	else if (hw->bus.func == E1000_FUNC_3)
401 566
 
		mask = E1000_SWFW_PHY3_SM;
402 567
 

	
403
 
	e1000_release_swfw_sync_82575(hw, mask);
568
 
	hw->mac.ops.release_swfw_sync(hw, mask);
404 569
 
}
405 570
 

	
406 571
 
/**
...
 
@@ -413,7 +578,7 @@ static void e1000_release_phy_82575(struct e1000_hw *hw)
413 578
 
 *  interface and stores the retrieved information in data.
414 579
 
 **/
415 580
 
static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
416
 
                                          u16 *data)
581
 
					  u16 *data)
417 582
 
{
418 583
 
	s32 ret_val = -E1000_ERR_PARAM;
419 584
 

	
...
 
@@ -446,7 +611,7 @@ out:
446 611
 
 *  media independent interface.
447 612
 
 **/
448 613
 
static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
449
 
                                           u16 data)
614
 
					   u16 data)
450 615
 
{
451 616
 
	s32 ret_val = -E1000_ERR_PARAM;
452 617
 

	
...
 
@@ -482,6 +647,7 @@ static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
482 647
 
	s32  ret_val = E1000_SUCCESS;
483 648
 
	u16 phy_id;
484 649
 
	u32 ctrl_ext;
650
 
	u32 mdic;
485 651
 

	
486 652
 
	DEBUGFUNC("e1000_get_phy_id_82575");
487 653
 

	
...
 
@@ -498,10 +664,36 @@ static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
498 664
 
		goto out;
499 665
 
	}
500 666
 

	
667
 
	if (e1000_sgmii_uses_mdio_82575(hw)) {
668
 
		switch (hw->mac.type) {
669
 
		case e1000_82575:
670
 
		case e1000_82576:
671
 
			mdic = E1000_READ_REG(hw, E1000_MDIC);
672
 
			mdic &= E1000_MDIC_PHY_MASK;
673
 
			phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
674
 
			break;
675
 
		case e1000_82580:
676
 
		case e1000_i350:
677
 
		case e1000_i354:
678
 
		case e1000_i210:
679
 
		case e1000_i211:
680
 
			mdic = E1000_READ_REG(hw, E1000_MDICNFG);
681
 
			mdic &= E1000_MDICNFG_PHY_MASK;
682
 
			phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
683
 
			break;
684
 
		default:
685
 
			ret_val = -E1000_ERR_PHY;
686
 
			goto out;
687
 
			break;
688
 
		}
689
 
		ret_val = e1000_get_phy_id(hw);
690
 
		goto out;
691
 
	}
692
 

	
501 693
 
	/* Power on sgmii phy if it is disabled */
502 694
 
	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
503 695
 
	E1000_WRITE_REG(hw, E1000_CTRL_EXT,
504
 
	                ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
696
 
			ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
505 697
 
	E1000_WRITE_FLUSH(hw);
506 698
 
	msec_delay(300);
507 699
 

	
...
 
@@ -513,8 +705,7 @@ static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
513 705
 
		ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
514 706
 
		if (ret_val == E1000_SUCCESS) {
515 707
 
			DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
516
 
			          phy_id,
517
 
			          phy->addr);
708
 
				  phy_id, phy->addr);
518 709
 
			/*
519 710
 
			 * At the time of this writing, The M88 part is
520 711
 
			 * the only supported SGMII PHY product.
...
 
@@ -523,7 +714,7 @@ static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
523 714
 
				break;
524 715
 
		} else {
525 716
 
			DEBUGOUT1("PHY address %u was unreadable\n",
526
 
			          phy->addr);
717
 
				  phy->addr);
527 718
 
		}
528 719
 
	}
529 720
 

	
...
 
@@ -609,22 +800,22 @@ static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
609 800
 
	if (active) {
610 801
 
		data |= IGP02E1000_PM_D0_LPLU;
611 802
 
		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
612
 
		                             data);
803
 
					     data);
613 804
 
		if (ret_val)
614 805
 
			goto out;
615 806
 

	
616 807
 
		/* When LPLU is enabled, we should disable SmartSpeed */
617 808
 
		ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
618
 
		                            &data);
809
 
					    &data);
619 810
 
		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
620 811
 
		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
621
 
		                             data);
812
 
					     data);
622 813
 
		if (ret_val)
623 814
 
			goto out;
624 815
 
	} else {
625 816
 
		data &= ~IGP02E1000_PM_D0_LPLU;
626 817
 
		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
627
 
		                             data);
818
 
					     data);
628 819
 
		/*
629 820
 
		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
630 821
 
		 * during Dx states where the power conservation is most
...
 
@@ -633,28 +824,28 @@ static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
633 824
 
		 */
634 825
 
		if (phy->smart_speed == e1000_smart_speed_on) {
635 826
 
			ret_val = phy->ops.read_reg(hw,
636
 
			                            IGP01E1000_PHY_PORT_CONFIG,
637
 
			                            &data);
827
 
						    IGP01E1000_PHY_PORT_CONFIG,
828
 
						    &data);
638 829
 
			if (ret_val)
639 830
 
				goto out;
640 831
 

	
641 832
 
			data |= IGP01E1000_PSCFR_SMART_SPEED;
642 833
 
			ret_val = phy->ops.write_reg(hw,
643
 
			                             IGP01E1000_PHY_PORT_CONFIG,
644
 
			                             data);
834
 
						     IGP01E1000_PHY_PORT_CONFIG,
835
 
						     data);
645 836
 
			if (ret_val)
646 837
 
				goto out;
647 838
 
		} else if (phy->smart_speed == e1000_smart_speed_off) {
648 839
 
			ret_val = phy->ops.read_reg(hw,
649
 
			                            IGP01E1000_PHY_PORT_CONFIG,
650
 
			                            &data);
840
 
						    IGP01E1000_PHY_PORT_CONFIG,
841
 
						    &data);
651 842
 
			if (ret_val)
652 843
 
				goto out;
653 844
 

	
654 845
 
			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
655 846
 
			ret_val = phy->ops.write_reg(hw,
656
 
			                             IGP01E1000_PHY_PORT_CONFIG,
657
 
			                             data);
847
 
						     IGP01E1000_PHY_PORT_CONFIG,
848
 
						     data);
658 849
 
			if (ret_val)
659 850
 
				goto out;
660 851
 
		}
...
 
@@ -665,6 +856,101 @@ out:
665 856
 
}
666 857
 

	
667 858
 
/**
859
 
 *  e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
860
 
 *  @hw: pointer to the HW structure
861
 
 *  @active: true to enable LPLU, false to disable
862
 
 *
863
 
 *  Sets the LPLU D0 state according to the active flag.  When
864
 
 *  activating LPLU this function also disables smart speed
865
 
 *  and vice versa.  LPLU will not be activated unless the
866
 
 *  device autonegotiation advertisement meets standards of
867
 
 *  either 10 or 10/100 or 10/100/1000 at all duplexes.
868
 
 *  This is a function pointer entry point only called by
869
 
 *  PHY setup routines.
870
 
 **/
871
 
static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
872
 
{
873
 
	struct e1000_phy_info *phy = &hw->phy;
874
 
	s32 ret_val = E1000_SUCCESS;
875
 
	u32 data;
876
 

	
877
 
	DEBUGFUNC("e1000_set_d0_lplu_state_82580");
878
 

	
879
 
	data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
880
 

	
881
 
	if (active) {
882
 
		data |= E1000_82580_PM_D0_LPLU;
883
 

	
884
 
		/* When LPLU is enabled, we should disable SmartSpeed */
885
 
		data &= ~E1000_82580_PM_SPD;
886
 
	} else {
887
 
		data &= ~E1000_82580_PM_D0_LPLU;
888
 

	
889
 
		/*
890
 
		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
891
 
		 * during Dx states where the power conservation is most
892
 
		 * important.  During driver activity we should enable
893
 
		 * SmartSpeed, so performance is maintained.
894
 
		 */
895
 
		if (phy->smart_speed == e1000_smart_speed_on)
896
 
			data |= E1000_82580_PM_SPD;
897
 
		else if (phy->smart_speed == e1000_smart_speed_off)
898
 
			data &= ~E1000_82580_PM_SPD;
899
 
	}
900
 

	
901
 
	E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
902
 
	return ret_val;
903
 
}
904
 

	
905
 
/**
906
 
 *  e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
907
 
 *  @hw: pointer to the HW structure
908
 
 *  @active: boolean used to enable/disable lplu
909
 
 *
910
 
 *  Success returns 0, Failure returns 1
911
 
 *
912
 
 *  The low power link up (lplu) state is set to the power management level D3
913
 
 *  and SmartSpeed is disabled when active is true, else clear lplu for D3
914
 
 *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
915
 
 *  is used during Dx states where the power conservation is most important.
916
 
 *  During driver activity, SmartSpeed should be enabled so performance is
917
 
 *  maintained.
918
 
 **/
919
 
s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
920
 
{
921
 
	struct e1000_phy_info *phy = &hw->phy;
922
 
	s32 ret_val = E1000_SUCCESS;
923
 
	u32 data;
924
 

	
925
 
	DEBUGFUNC("e1000_set_d3_lplu_state_82580");
926
 

	
927
 
	data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
928
 

	
929
 
	if (!active) {
930
 
		data &= ~E1000_82580_PM_D3_LPLU;
931
 
		/*
932
 
		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
933
 
		 * during Dx states where the power conservation is most
934
 
		 * important.  During driver activity we should enable
935
 
		 * SmartSpeed, so performance is maintained.
936
 
		 */
937
 
		if (phy->smart_speed == e1000_smart_speed_on)
938
 
			data |= E1000_82580_PM_SPD;
939
 
		else if (phy->smart_speed == e1000_smart_speed_off)
940
 
			data &= ~E1000_82580_PM_SPD;
941
 
	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
942
 
		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
943
 
		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
944
 
		data |= E1000_82580_PM_D3_LPLU;
945
 
		/* When LPLU is enabled, we should disable SmartSpeed */
946
 
		data &= ~E1000_82580_PM_SPD;
947
 
	}
948
 

	
949
 
	E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
950
 
	return ret_val;
951
 
}
952
 

	
953
 
/**
668 954
 
 *  e1000_acquire_nvm_82575 - Request for access to EEPROM
669 955
 
 *  @hw: pointer to the HW structure
670 956
 
 *
...
 
@@ -683,8 +969,32 @@ static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
683 969
 
	if (ret_val)
684 970
 
		goto out;
685 971
 

	
686
 
	ret_val = e1000_acquire_nvm_generic(hw);
972
 
	/*
973
 
	 * Check if there is some access
974
 
	 * error this access may hook on
975
 
	 */
976
 
	if (hw->mac.type == e1000_i350) {
977
 
		u32 eecd = E1000_READ_REG(hw, E1000_EECD);
978
 
		if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
979
 
		    E1000_EECD_TIMEOUT)) {
980
 
			/* Clear all access error flags */
981
 
			E1000_WRITE_REG(hw, E1000_EECD, eecd |
982
 
					E1000_EECD_ERROR_CLR);
983
 
			DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
984
 
		}
985
 
	}
986
 
	if (hw->mac.type == e1000_82580) {
987
 
		u32 eecd = E1000_READ_REG(hw, E1000_EECD);
988
 
		if (eecd & E1000_EECD_BLOCKED) {
989
 
			/* Clear access error flag */
990
 
			E1000_WRITE_REG(hw, E1000_EECD, eecd |
991
 
					E1000_EECD_BLOCKED);
992
 
			DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
993
 
		}
994
 
	}
995
 

	
687 996
 

	
997
 
	ret_val = e1000_acquire_nvm_generic(hw);
688 998
 
	if (ret_val)
689 999
 
		e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
690 1000
 

	
...
 
@@ -704,6 +1014,7 @@ static void e1000_release_nvm_82575(struct e1000_hw *hw)
704 1014
 
	DEBUGFUNC("e1000_release_nvm_82575");
705 1015
 

	
706 1016
 
	e1000_release_nvm_generic(hw);
1017
 

	
707 1018
 
	e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
708 1019
 
}
709 1020
 

	
...
 
@@ -773,8 +1084,8 @@ static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
773 1084
 

	
774 1085
 
	DEBUGFUNC("e1000_release_swfw_sync_82575");
775 1086
 

	
776
 
	while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS);
777
 
	/* Empty */
1087
 
	while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1088
 
		; /* Empty */
778 1089
 

	
779 1090
 
	swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
780 1091
 
	swfw_sync &= ~mask;
...
 
@@ -817,7 +1128,7 @@ static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
817 1128
 
		DEBUGOUT("MNG configuration cycle has not completed.\n");
818 1129
 

	
819 1130
 
	/* If EEPROM is not marked present, init the PHY manually */
820
 
	if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
1131
 
	if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
821 1132
 
	    (hw->phy.type == e1000_phy_igp_3))
822 1133
 
		e1000_phy_init_script_igp3(hw);
823 1134
 

	
...
 
@@ -835,7 +1146,7 @@ static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
835 1146
 
 *  Otherwise, use the generic function to get the link speed and duplex info.
836 1147
 
 **/
837 1148
 
static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
838
 
                                        u16 *duplex)
1149
 
					u16 *duplex)
839 1150
 
{
840 1151
 
	s32 ret_val;
841 1152
 

	
...
 
@@ -843,10 +1154,10 @@ static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
843 1154
 

	
844 1155
 
	if (hw->phy.media_type != e1000_media_type_copper)
845 1156
 
		ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
846
 
		                                               duplex);
1157
 
							       duplex);
847 1158
 
	else
848 1159
 
		ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
849
 
		                                                    duplex);
1160
 
								    duplex);
850 1161
 

	
851 1162
 
	return ret_val;
852 1163
 
}
...
 
@@ -867,13 +1178,23 @@ static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
867 1178
 

	
868 1179
 
	if (hw->phy.media_type != e1000_media_type_copper) {
869 1180
 
		ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
870
 
		                                               &duplex);
1181
 
							       &duplex);
871 1182
 
		/*
872 1183
 
		 * Use this flag to determine if link needs to be checked or
873 1184
 
		 * not.  If we have link clear the flag so that we do not
874 1185
 
		 * continue to check for link.
875 1186
 
		 */
876 1187
 
		hw->mac.get_link_status = !hw->mac.serdes_has_link;
1188
 

	
1189
 
		/*
1190
 
		 * Configure Flow Control now that Auto-Neg has completed.
1191
 
		 * First, we need to restore the desired flow control
1192
 
		 * settings because we may have had to re-autoneg with a
1193
 
		 * different link partner.
1194
 
		 */
1195
 
		ret_val = e1000_config_fc_after_link_up_generic(hw);
1196
 
		if (ret_val)
1197
 
			DEBUGOUT("Error configuring flow control\n");
877 1198
 
	} else {
878 1199
 
		ret_val = e1000_check_for_copper_link_generic(hw);
879 1200
 
	}
...
 
@@ -882,6 +1203,85 @@ static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
882 1203
 
}
883 1204
 

	
884 1205
 
/**
1206
 
 *  e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1207
 
 *  @hw: pointer to the HW structure
1208
 
 *
1209
 
 *  Poll the M88E1112 interfaces to see which interface achieved link.
1210
 
 */
1211
 
static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1212
 
{
1213
 
	struct e1000_phy_info *phy = &hw->phy;
1214
 
	s32 ret_val;
1215
 
	u16 data;
1216
 
	u8 port = 0;
1217
 

	
1218
 
	DEBUGFUNC("e1000_check_for_link_media_swap");
1219
 

	
1220
 
	/* Check the copper medium. */
1221
 
	ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1222
 
	if (ret_val)
1223
 
		return ret_val;
1224
 

	
1225
 
	ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1226
 
	if (ret_val)
1227
 
		return ret_val;
1228
 

	
1229
 
	if (data & E1000_M88E1112_STATUS_LINK)
1230
 
		port = E1000_MEDIA_PORT_COPPER;
1231
 

	
1232
 
	/* Check the other medium. */
1233
 
	ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1234
 
	if (ret_val)
1235
 
		return ret_val;
1236
 

	
1237
 
	ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1238
 
	if (ret_val)
1239
 
		return ret_val;
1240
 

	
1241
 
	if (data & E1000_M88E1112_STATUS_LINK)
1242
 
		port = E1000_MEDIA_PORT_OTHER;
1243
 

	
1244
 
	/* Determine if a swap needs to happen. */
1245
 
	if (port && (hw->dev_spec._82575.media_port != port)) {
1246
 
		hw->dev_spec._82575.media_port = port;
1247
 
		hw->dev_spec._82575.media_changed = true;
1248
 
	} else {
1249
 
		ret_val = e1000_check_for_link_82575(hw);
1250
 
	}
1251
 

	
1252
 
	return E1000_SUCCESS;
1253
 
}
1254
 

	
1255
 
/**
1256
 
 *  e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1257
 
 *  @hw: pointer to the HW structure
1258
 
 **/
1259
 
static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1260
 
{
1261
 
	u32 reg;
1262
 

	
1263
 
	DEBUGFUNC("e1000_power_up_serdes_link_82575");
1264
 

	
1265
 
	if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1266
 
	    !e1000_sgmii_active_82575(hw))
1267
 
		return;
1268
 

	
1269
 
	/* Enable PCS to turn on link */
1270
 
	reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1271
 
	reg |= E1000_PCS_CFG_PCS_EN;
1272
 
	E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1273
 

	
1274
 
	/* Power up the laser */
1275
 
	reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1276
 
	reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1277
 
	E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1278
 

	
1279
 
	/* flush the write to verify completion */
1280
 
	E1000_WRITE_FLUSH(hw);
1281
 
	msec_delay(1);
1282
 
}
1283
 

	
1284
 
/**
885 1285
 
 *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
886 1286
 
 *  @hw: pointer to the HW structure
887 1287
 
 *  @speed: stores the current speed
...
 
@@ -891,18 +1291,14 @@ static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
891 1291
 
 *  duplex, then store the values in the pointers provided.
892 1292
 
 **/
893 1293
 
static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
894
 
                                                u16 *speed, u16 *duplex)
1294
 
						u16 *speed, u16 *duplex)
895 1295
 
{
896 1296
 
	struct e1000_mac_info *mac = &hw->mac;
897 1297
 
	u32 pcs;
1298
 
	u32 status;
898 1299
 

	
899 1300
 
	DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
900 1301
 

	
901
 
	/* Set up defaults for the return values of this function */
902
 
	mac->serdes_has_link = false;
903
 
	*speed = 0;
904
 
	*duplex = 0;
905
 

	
906 1302
 
	/*
907 1303
 
	 * Read the PCS Status register for link state. For non-copper mode,
908 1304
 
	 * the status register is not accurate. The PCS status register is
...
 
@@ -911,28 +1307,41 @@ static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
911 1307
 
	pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
912 1308
 

	
913 1309
 
	/*
914
 
	 * The link up bit determines when link is up on autoneg. The sync ok
915
 
	 * gets set once both sides sync up and agree upon link. Stable link
916
 
	 * can be determined by checking for both link up and link sync ok
1310
 
	 * The link up bit determines when link is up on autoneg.
917 1311
 
	 */
918
 
	if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1312
 
	if (pcs & E1000_PCS_LSTS_LINK_OK) {
919 1313
 
		mac->serdes_has_link = true;
920 1314
 

	
921 1315
 
		/* Detect and store PCS speed */
922
 
		if (pcs & E1000_PCS_LSTS_SPEED_1000) {
1316
 
		if (pcs & E1000_PCS_LSTS_SPEED_1000)
923 1317
 
			*speed = SPEED_1000;
924
 
		} else if (pcs & E1000_PCS_LSTS_SPEED_100) {
1318
 
		else if (pcs & E1000_PCS_LSTS_SPEED_100)
925 1319
 
			*speed = SPEED_100;
926
 
		} else {
1320
 
		else
927 1321
 
			*speed = SPEED_10;
928
 
		}
929 1322
 

	
930 1323
 
		/* Detect and store PCS duplex */
931
 
		if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
1324
 
		if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
932 1325
 
			*duplex = FULL_DUPLEX;
933
 
		} else {
1326
 
		else
934 1327
 
			*duplex = HALF_DUPLEX;
1328
 

	
1329
 
		/* Check if it is an I354 2.5Gb backplane connection. */
1330
 
		if (mac->type == e1000_i354) {
1331
 
			status = E1000_READ_REG(hw, E1000_STATUS);
1332
 
			if ((status & E1000_STATUS_2P5_SKU) &&
1333
 
			    !(status & E1000_STATUS_2P5_SKU_OVER)) {
1334
 
				*speed = SPEED_2500;
1335
 
				*duplex = FULL_DUPLEX;
1336
 
				DEBUGOUT("2500 Mbs, ");
1337
 
				DEBUGOUT("Full Duplex\n");
1338
 
			}
935 1339
 
		}
1340
 

	
1341
 
	} else {
1342
 
		mac->serdes_has_link = false;
1343
 
		*speed = 0;
1344
 
		*duplex = 0;
936 1345
 
	}
937 1346
 

	
938 1347
 
	return E1000_SUCCESS;
...
 
@@ -948,27 +1357,14 @@ static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
948 1357
 
void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
949 1358
 
{
950 1359
 
	u32 reg;
951
 
	u16 eeprom_data = 0;
1360
 

	
1361
 
	DEBUGFUNC("e1000_shutdown_serdes_link_82575");
952 1362
 

	
953 1363
 
	if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
954 1364
 
	    !e1000_sgmii_active_82575(hw))
955 1365
 
		return;
956 1366
 

	
957
 
	if (hw->bus.func == E1000_FUNC_0)
958
 
		hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
959
 
	else if (hw->mac.type == e1000_82580)
960
 
		hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
961
 
		                 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
962
 
		                 &eeprom_data);
963
 
	else if (hw->bus.func == E1000_FUNC_1)
964
 
		hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
965
 

	
966
 
	/*
967
 
	 * If APM is not enabled in the EEPROM and management interface is
968
 
	 * not enabled, then power down.
969
 
	 */
970
 
	if (!(eeprom_data & E1000_NVM_APME_82575) &&
971
 
	    !e1000_enable_mng_pass_thru(hw)) {
1367
 
	if (!e1000_enable_mng_pass_thru(hw)) {
972 1368
 
		/* Disable PCS to turn off link */
973 1369
 
		reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
974 1370
 
		reg &= ~E1000_PCS_CFG_PCS_EN;
...
 
@@ -995,7 +1391,7 @@ void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
995 1391
 
 **/
996 1392
 
static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
997 1393
 
{
998
 
	u32 ctrl, icr;
1394
 
	u32 ctrl;
999 1395
 
	s32 ret_val;
1000 1396
 

	
1001 1397
 
	DEBUGFUNC("e1000_reset_hw_82575");
...
 
@@ -1005,15 +1401,13 @@ static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1005 1401
 
	 * on the last TLP read/write transaction when MAC is reset.
1006 1402
 
	 */
1007 1403
 
	ret_val = e1000_disable_pcie_master_generic(hw);
1008
 
	if (ret_val) {
1404
 
	if (ret_val)
1009 1405
 
		DEBUGOUT("PCI-E Master disable polling has failed.\n");
1010
 
	}
1011 1406
 

	
1012 1407
 
	/* set the completion timeout for interface */
1013 1408
 
	ret_val = e1000_set_pcie_completion_timeout(hw);
1014
 
	if (ret_val) {
1409
 
	if (ret_val)
1015 1410
 
		DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1016
 
	}
1017 1411
 

	
1018 1412
 
	DEBUGOUT("Masking off all interrupts\n");
1019 1413
 
	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
...
 
@@ -1040,12 +1434,12 @@ static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1040 1434
 
	}
1041 1435
 

	
1042 1436
 
	/* If EEPROM is not present, run manual init scripts */
1043
 
	if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0)
1437
 
	if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1044 1438
 
		e1000_reset_init_script_82575(hw);
1045 1439
 

	
1046 1440
 
	/* Clear any pending interrupt events. */
1047 1441
 
	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1048
 
	icr = E1000_READ_REG(hw, E1000_ICR);
1442
 
	E1000_READ_REG(hw, E1000_ICR);
1049 1443
 

	
1050 1444
 
	/* Install any alternate MAC address into RAR0 */
1051 1445
 
	ret_val = e1000_check_alt_mac_addr_generic(hw);
...
 
@@ -1094,6 +1488,9 @@ static s32 e1000_init_hw_82575(struct e1000_hw *hw)
1094 1488
 
	/* Setup link and flow control */
1095 1489
 
	ret_val = mac->ops.setup_link(hw);
1096 1490
 

	
1491
 
	/* Set the default MTU size */
1492
 
	hw->dev_spec._82575.mtu = 1500;
1493
 

	
1097 1494
 
	/*
1098 1495
 
	 * Clear all of the statistics registers (clear on read).  It is
1099 1496
 
	 * important that we do this after we have tried to establish link
...
 
@@ -1116,7 +1513,8 @@ static s32 e1000_init_hw_82575(struct e1000_hw *hw)
1116 1513
 
static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1117 1514
 
{
1118 1515
 
	u32 ctrl;
1119
 
	s32  ret_val;
1516
 
	s32 ret_val;
1517
 
	u32 phpm_reg;
1120 1518
 

	
1121 1519
 
	DEBUGFUNC("e1000_setup_copper_link_82575");
1122 1520
 

	
...
 
@@ -1125,6 +1523,20 @@ static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1125 1523
 
	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1126 1524
 
	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1127 1525
 

	
1526
 
	/* Clear Go Link Disconnect bit on supported devices */
1527
 
	switch (hw->mac.type) {
1528
 
	case e1000_82580:
1529
 
	case e1000_i350:
1530
 
	case e1000_i210:
1531
 
	case e1000_i211:
1532
 
		phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1533
 
		phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1534
 
		E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1535
 
		break;
1536
 
	default:
1537
 
		break;
1538
 
	}
1539
 

	
1128 1540
 
	ret_val = e1000_setup_serdes_link_82575(hw);
1129 1541
 
	if (ret_val)
1130 1542
 
		goto out;
...
 
@@ -1140,8 +1552,20 @@ static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1140 1552
 
		}
1141 1553
 
	}
1142 1554
 
	switch (hw->phy.type) {
1555
 
	case e1000_phy_i210:
1143 1556
 
	case e1000_phy_m88:
1144
 
		ret_val = e1000_copper_link_setup_m88(hw);
1557
 
		switch (hw->phy.id) {
1558
 
		case I347AT4_E_PHY_ID:
1559
 
		case M88E1112_E_PHY_ID:
1560
 
		case M88E1340M_E_PHY_ID:
1561
 
		case M88E1543_E_PHY_ID:
1562
 
		case I210_I_PHY_ID:
1563
 
			ret_val = e1000_copper_link_setup_m88_gen2(hw);
1564
 
			break;
1565
 
		default:
1566
 
			ret_val = e1000_copper_link_setup_m88(hw);
1567
 
			break;
1568
 
		}
1145 1569
 
		break;
1146 1570
 
	case e1000_phy_igp_3:
1147 1571
 
		ret_val = e1000_copper_link_setup_igp(hw);
...
 
@@ -1173,14 +1597,16 @@ out:
1173 1597
 
 **/
1174 1598
 
static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1175 1599
 
{
1176
 
	u32 ctrl_ext, ctrl_reg, reg;
1600
 
	u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1177 1601
 
	bool pcs_autoneg;
1602
 
	s32 ret_val = E1000_SUCCESS;
1603
 
	u16 data;
1178 1604
 

	
1179 1605
 
	DEBUGFUNC("e1000_setup_serdes_link_82575");
1180 1606
 

	
1181 1607
 
	if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1182 1608
 
	    !e1000_sgmii_active_82575(hw))
1183
 
		return E1000_SUCCESS;
1609
 
		return ret_val;
1184 1610
 

	
1185 1611
 
	/*
1186 1612
 
	 * On the 82575, SerDes loopback mode persists until it is
...
 
@@ -1198,16 +1624,10 @@ static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1198 1624
 
	ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1199 1625
 
	ctrl_reg |= E1000_CTRL_SLU;
1200 1626
 

	
1201
 
	if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1202
 
		/* set both sw defined pins */
1627
 
	/* set both sw defined pins on 82575/82576*/
1628
 
	if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1203 1629
 
		ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1204 1630
 

	
1205
 
		/* Set switch control to serdes energy detect */
1206
 
		reg = E1000_READ_REG(hw, E1000_CONNSW);
1207
 
		reg |= E1000_CONNSW_ENRGSRC;
1208
 
		E1000_WRITE_REG(hw, E1000_CONNSW, reg);
1209
 
	}
1210
 

	
1211 1631
 
	reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1212 1632
 

	
1213 1633
 
	/* default pcs_autoneg to the same setting as mac autoneg */
...
 
@@ -1223,14 +1643,27 @@ static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1223 1643
 
	case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1224 1644
 
		/* disable PCS autoneg and support parallel detect only */
1225 1645
 
		pcs_autoneg = false;
1646
 
		/* fall through to default case */
1226 1647
 
	default:
1227
 
		/*
1648
 
		if (hw->mac.type == e1000_82575 ||
1649
 
		    hw->mac.type == e1000_82576) {
1650
 
			ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1651
 
			if (ret_val) {
1652
 
				DEBUGOUT("NVM Read Error\n");
1653
 
				return ret_val;
1654
 
			}
1655
 

	
1656
 
			if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1657
 
				pcs_autoneg = false;
1658
 
		}
1659
 

	
1660
 
		/*
1228 1661
 
		 * non-SGMII modes only supports a speed of 1000/Full for the
1229 1662
 
		 * link so it is best to just force the MAC and let the pcs
1230 1663
 
		 * link either autoneg or be forced to 1000/Full
1231 1664
 
		 */
1232 1665
 
		ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1233
 
		            E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1666
 
			    E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1234 1667
 

	
1235 1668
 
		/* set speed of 1000/Full if speed/duplex is forced */
1236 1669
 
		reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
...
 
@@ -1246,31 +1679,203 @@ static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1246 1679
 
	 * However, both are supported by the hardware and some drivers/tools.
1247 1680
 
	 */
1248 1681
 
	reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1249
 
	         E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1250
 

	
1251
 
	/*
1252
 
	 * We force flow control to prevent the CTRL register values from being
1253
 
	 * overwritten by the autonegotiated flow control values
1254
 
	 */
1255
 
	reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1682
 
		 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1256 1683
 

	
1257 1684
 
	if (pcs_autoneg) {
1258 1685
 
		/* Set PCS register for autoneg */
1259 1686
 
		reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1260 1687
 
		       E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1688
 

	
1689
 
		/* Disable force flow control for autoneg */
1690
 
		reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1691
 

	
1692
 
		/* Configure flow control advertisement for autoneg */
1693
 
		anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1694
 
		anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1695
 

	
1696
 
		switch (hw->fc.requested_mode) {
1697
 
		case e1000_fc_full:
1698
 
		case e1000_fc_rx_pause:
1699
 
			anadv_reg |= E1000_TXCW_ASM_DIR;
1700
 
			anadv_reg |= E1000_TXCW_PAUSE;
1701
 
			break;
1702
 
		case e1000_fc_tx_pause:
1703
 
			anadv_reg |= E1000_TXCW_ASM_DIR;
1704
 
			break;
1705
 
		default:
1706
 
			break;
1707
 
		}
1708
 

	
1709
 
		E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1710
 

	
1261 1711
 
		DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1262 1712
 
	} else {
1263 1713
 
		/* Set PCS register for forced link */
1264
 
		reg |= E1000_PCS_LCTL_FSD;        /* Force Speed */
1714
 
		reg |= E1000_PCS_LCTL_FSD;	/* Force Speed */
1715
 

	
1716
 
		/* Force flow control for forced link */
1717
 
		reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1718
 

	
1265 1719
 
		DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1266 1720
 
	}
1267 1721
 

	
1268 1722
 
	E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1269 1723
 

	
1270
 
	if (!e1000_sgmii_active_82575(hw))
1724
 
	if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1271 1725
 
		e1000_force_mac_fc_generic(hw);
1272 1726
 

	
1273
 
	return E1000_SUCCESS;
1727
 
	return ret_val;
1728
 
}
1729
 

	
1730
 
/**
1731
 
 *  e1000_get_media_type_82575 - derives current media type.
1732
 
 *  @hw: pointer to the HW structure
1733
 
 *
1734
 
 *  The media type is chosen reflecting few settings.
1735
 
 *  The following are taken into account:
1736
 
 *  - link mode set in the current port Init Control Word #3
1737
 
 *  - current link mode settings in CSR register
1738
 
 *  - MDIO vs. I2C PHY control interface chosen
1739
 
 *  - SFP module media type
1740
 
 **/
1741
 
static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1742
 
{
1743
 
	struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1744
 
	s32 ret_val = E1000_SUCCESS;
1745
 
	u32 ctrl_ext = 0;
1746
 
	u32 link_mode = 0;
1747
 

	
1748
 
	/* Set internal phy as default */
1749
 
	dev_spec->sgmii_active = false;
1750
 
	dev_spec->module_plugged = false;
1751
 

	
1752
 
	/* Get CSR setting */
1753
 
	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1754
 

	
1755
 
	/* extract link mode setting */
1756
 
	link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1757
 

	
1758
 
	switch (link_mode) {
1759
 
	case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1760
 
		hw->phy.media_type = e1000_media_type_internal_serdes;
1761
 
		break;
1762
 
	case E1000_CTRL_EXT_LINK_MODE_GMII:
1763
 
		hw->phy.media_type = e1000_media_type_copper;
1764
 
		break;
1765
 
	case E1000_CTRL_EXT_LINK_MODE_SGMII:
1766
 
		/* Get phy control interface type set (MDIO vs. I2C)*/
1767
 
		if (e1000_sgmii_uses_mdio_82575(hw)) {
1768
 
			hw->phy.media_type = e1000_media_type_copper;
1769
 
			dev_spec->sgmii_active = true;
1770
 
			break;
1771
 
		}
1772
 
		/* fall through for I2C based SGMII */
1773
 
	case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1774
 
		/* read media type from SFP EEPROM */
1775
 
		ret_val = e1000_set_sfp_media_type_82575(hw);
1776
 
		if ((ret_val != E1000_SUCCESS) ||
1777
 
		    (hw->phy.media_type == e1000_media_type_unknown)) {
1778
 
			/*
1779
 
			 * If media type was not identified then return media
1780
 
			 * type defined by the CTRL_EXT settings.
1781
 
			 */
1782
 
			hw->phy.media_type = e1000_media_type_internal_serdes;
1783
 

	
1784
 
			if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1785
 
				hw->phy.media_type = e1000_media_type_copper;
1786
 
				dev_spec->sgmii_active = true;
1787
 
			}
1788
 

	
1789
 
			break;
1790
 
		}
1791
 

	
1792
 
		/* do not change link mode for 100BaseFX */
1793
 
		if (dev_spec->eth_flags.e100_base_fx)
1794
 
			break;
1795
 

	
1796
 
		/* change current link mode setting */
1797
 
		ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1798
 

	
1799
 
		if (hw->phy.media_type == e1000_media_type_copper)
1800
 
			ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1801
 
		else
1802
 
			ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1803
 

	
1804
 
		E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1805
 

	
1806
 
		break;
1807
 
	}
1808
 

	
1809
 
	return ret_val;
1810
 
}
1811
 

	
1812
 
/**
1813
 
 *  e1000_set_sfp_media_type_82575 - derives SFP module media type.
1814
 
 *  @hw: pointer to the HW structure
1815
 
 *
1816
 
 *  The media type is chosen based on SFP module.
1817
 
 *  compatibility flags retrieved from SFP ID EEPROM.
1818
 
 **/
1819
 
static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1820
 
{
1821
 
	s32 ret_val = E1000_ERR_CONFIG;
1822
 
	u32 ctrl_ext = 0;
1823
 
	struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1824
 
	struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1825
 
	u8 tranceiver_type = 0;
1826
 
	s32 timeout = 3;
1827
 

	
1828
 
	/* Turn I2C interface ON and power on sfp cage */
1829
 
	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1830
 
	ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1831
 
	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1832
 

	
1833
 
	E1000_WRITE_FLUSH(hw);
1834
 

	
1835
 
	/* Read SFP module data */
1836
 
	while (timeout) {
1837
 
		ret_val = e1000_read_sfp_data_byte(hw,
1838
 
			E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1839
 
			&tranceiver_type);
1840
 
		if (ret_val == E1000_SUCCESS)
1841
 
			break;
1842
 
		msec_delay(100);
1843
 
		timeout--;
1844
 
	}
1845
 
	if (ret_val != E1000_SUCCESS)
1846
 
		goto out;
1847
 

	
1848
 
	ret_val = e1000_read_sfp_data_byte(hw,
1849
 
			E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1850
 
			(u8 *)eth_flags);
1851
 
	if (ret_val != E1000_SUCCESS)
1852
 
		goto out;
1853
 

	
1854
 
	/* Check if there is some SFP module plugged and powered */
1855
 
	if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1856
 
	    (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1857
 
		dev_spec->module_plugged = true;
1858
 
		if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1859
 
			hw->phy.media_type = e1000_media_type_internal_serdes;
1860
 
		} else if (eth_flags->e100_base_fx) {
1861
 
			dev_spec->sgmii_active = true;
1862
 
			hw->phy.media_type = e1000_media_type_internal_serdes;
1863
 
		} else if (eth_flags->e1000_base_t) {
1864
 
			dev_spec->sgmii_active = true;
1865
 
			hw->phy.media_type = e1000_media_type_copper;
1866
 
		} else {
1867
 
			hw->phy.media_type = e1000_media_type_unknown;
1868
 
			DEBUGOUT("PHY module has not been recognized\n");
1869
 
			goto out;
1870
 
		}
1871
 
	} else {
1872
 
		hw->phy.media_type = e1000_media_type_unknown;
1873
 
	}
1874
 
	ret_val = E1000_SUCCESS;
1875
 
out:
1876
 
	/* Restore I2C interface setting */
1877
 
	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1878
 
	return ret_val;
1274 1879
 
}
1275 1880
 

	
1276 1881
 
/**
...
 
@@ -1294,7 +1899,7 @@ static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1294 1899
 
	}
1295 1900
 

	
1296 1901
 
	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1297
 
		switch(hw->phy.media_type) {
1902
 
		switch (hw->phy.media_type) {
1298 1903
 
		case e1000_media_type_internal_serdes:
1299 1904
 
			*data = ID_LED_DEFAULT_82575_SERDES;
1300 1905
 
			break;
...
 
@@ -1329,7 +1934,7 @@ static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1329 1934
 
 *  Inits recommended HW defaults after a reset when there is no EEPROM
1330 1935
 
 *  detected. This is only for the 82575.
1331 1936
 
 **/
1332
 
static s32 e1000_reset_init_script_82575(struct e1000_hw* hw)
1937
 
static s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1333 1938
 
{
1334 1939
 
	DEBUGFUNC("e1000_reset_init_script_82575");
1335 1940
 

	
...
 
@@ -1386,6 +1991,28 @@ out:
1386 1991
 
}
1387 1992
 

	
1388 1993
 
/**
1994
 
 *  e1000_config_collision_dist_82575 - Configure collision distance
1995
 
 *  @hw: pointer to the HW structure
1996
 
 *
1997
 
 *  Configures the collision distance to the default value and is used
1998
 
 *  during link setup.
1999
 
 **/
2000
 
static void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2001
 
{
2002
 
	u32 tctl_ext;
2003
 

	
2004
 
	DEBUGFUNC("e1000_config_collision_dist_82575");
2005
 

	
2006
 
	tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2007
 

	
2008
 
	tctl_ext &= ~E1000_TCTL_EXT_COLD;
2009
 
	tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2010
 

	
2011
 
	E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2012
 
	E1000_WRITE_FLUSH(hw);
2013
 
}
2014
 

	
2015
 
/**
1389 2016
 
 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
1390 2017
 
 * @hw: pointer to the HW structure
1391 2018
 
 *
...
 
@@ -1395,13 +2022,12 @@ out:
1395 2022
 
static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
1396 2023
 
{
1397 2024
 
	struct e1000_phy_info *phy = &hw->phy;
1398
 
	struct e1000_mac_info *mac = &hw->mac;
1399 2025
 

	
1400 2026
 
	if (!(phy->ops.check_reset_block))
1401 2027
 
		return;
1402 2028
 

	
1403 2029
 
	/* If the management interface is not enabled, then power down */
1404
 
	if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
2030
 
	if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
1405 2031
 
		e1000_power_down_phy_copper(hw);
1406 2032
 

	
1407 2033
 
	return;
...
 
@@ -1473,7 +2099,7 @@ static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
1473 2099
 
}
1474 2100
 

	
1475 2101
 
/**
1476
 
 *  e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable
2102
 
 *  e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
1477 2103
 
 *  @hw: pointer to the HW structure
1478 2104
 
 *
1479 2105
 
 *  After rx enable if managability is enabled then there is likely some
...
 
@@ -1491,11 +2117,11 @@ void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
1491 2117
 
	    !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1492 2118
 
		return;
1493 2119
 

	
1494
 
	/* Disable all RX queues */
2120
 
	/* Disable all Rx queues */
1495 2121
 
	for (i = 0; i < 4; i++) {
1496 2122
 
		rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
1497 2123
 
		E1000_WRITE_REG(hw, E1000_RXDCTL(i),
1498
 
		                rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2124
 
				rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1499 2125
 
	}
1500 2126
 
	/* Poll all queues to verify they have shut down */
1501 2127
 
	for (ms_wait = 0; ms_wait < 10; ms_wait++) {
...
 
@@ -1529,7 +2155,7 @@ void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
1529 2155
 
	E1000_WRITE_FLUSH(hw);
1530 2156
 
	msec_delay(2);
1531 2157
 

	
1532
 
	/* Enable RX queues that were previously enabled and restore our
2158
 
	/* Enable Rx queues that were previously enabled and restore our
1533 2159
 
	 * previous state
1534 2160
 
	 */
1535 2161
 
	for (i = 0; i < 4; i++)
...
 
@@ -1581,14 +2207,14 @@ static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
1581 2207
 
	 * 16ms to 55ms
1582 2208
 
	 */
1583 2209
 
	ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1584
 
	                                  &pcie_devctl2);
2210
 
					  &pcie_devctl2);
1585 2211
 
	if (ret_val)
1586 2212
 
		goto out;
1587 2213
 

	
1588 2214
 
	pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1589 2215
 

	
1590 2216
 
	ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1591
 
	                                   &pcie_devctl2);
2217
 
					   &pcie_devctl2);
1592 2218
 
out:
1593 2219
 
	/* disable completion timeout resend */
1594 2220
 
	gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
...
 
@@ -1598,6 +2224,45 @@ out:
1598 2224
 
}
1599 2225
 

	
1600 2226
 
/**
2227
 
 *  e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2228
 
 *  @hw: pointer to the hardware struct
2229
 
 *  @enable: state to enter, either enabled or disabled
2230
 
 *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2231
 
 *
2232
 
 *  enables/disables L2 switch anti-spoofing functionality.
2233
 
 **/
2234
 
void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2235
 
{
2236
 
	u32 reg_val, reg_offset;
2237
 

	
2238
 
	switch (hw->mac.type) {
2239
 
	case e1000_82576:
2240
 
		reg_offset = E1000_DTXSWC;
2241
 
		break;
2242
 
	case e1000_i350:
2243
 
	case e1000_i354:
2244
 
		reg_offset = E1000_TXSWC;
2245
 
		break;
2246
 
	default:
2247
 
		return;
2248
 
	}
2249
 

	
2250
 
	reg_val = E1000_READ_REG(hw, reg_offset);
2251
 
	if (enable) {
2252
 
		reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2253
 
			     E1000_DTXSWC_VLAN_SPOOF_MASK);
2254
 
		/* The PF can spoof - it has to in order to
2255
 
		 * support emulation mode NICs
2256
 
		 */
2257
 
		reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2258
 
	} else {
2259
 
		reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2260
 
			     E1000_DTXSWC_VLAN_SPOOF_MASK);
2261
 
	}
2262
 
	E1000_WRITE_REG(hw, reg_offset, reg_val);
2263
 
}
2264
 

	
2265
 
/**
1601 2266
 
 *  e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
1602 2267
 
 *  @hw: pointer to the hardware struct
1603 2268
 
 *  @enable: state to enter, either enabled or disabled
...
 
@@ -1606,14 +2271,32 @@ out:
1606 2271
 
 **/
1607 2272
 
void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1608 2273
 
{
1609
 
	u32 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2274
 
	u32 dtxswc;
2275
 

	
2276
 
	switch (hw->mac.type) {
2277
 
	case e1000_82576:
2278
 
		dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2279
 
		if (enable)
2280
 
			dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2281
 
		else
2282
 
			dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2283
 
		E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2284
 
		break;
2285
 
	case e1000_i350:
2286
 
	case e1000_i354:
2287
 
		dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2288
 
		if (enable)
2289
 
			dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2290
 
		else
2291
 
			dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2292
 
		E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2293
 
		break;
2294
 
	default:
2295
 
		/* Currently no other hardware supports loopback */
2296
 
		break;
2297
 
	}
1610 2298
 

	
1611
 
	if (enable)
1612
 
		dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1613
 
	else
1614
 
		dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1615 2299
 

	
1616
 
	E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
1617 2300
 
}
1618 2301
 

	
1619 2302
 
/**
...
 
@@ -1646,7 +2329,6 @@ void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1646 2329
 
 **/
1647 2330
 
static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1648 2331
 
{
1649
 
	u32 mdicnfg = 0;
1650 2332
 
	s32 ret_val;
1651 2333
 

	
1652 2334
 
	DEBUGFUNC("e1000_read_phy_reg_82580");
...
 
@@ -1655,15 +2337,6 @@ static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1655 2337
 
	if (ret_val)
1656 2338
 
		goto out;
1657 2339
 

	
1658
 
	/*
1659
 
	 * We config the phy address in MDICNFG register now. Same bits
1660
 
	 * as before. The values in MDIC can be written but will be
1661
 
	 * ignored. This allows us to call the old function after
1662
 
	 * configuring the PHY address in the new register
1663
 
	 */
1664
 
	mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT);
1665
 
	E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
1666
 

	
1667 2340
 
	ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
1668 2341
 

	
1669 2342
 
	hw->phy.ops.release(hw);
...
 
@@ -1682,7 +2355,6 @@ out:
1682 2355
 
 **/
1683 2356
 
static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
1684 2357
 
{
1685
 
	u32 mdicnfg = 0;
1686 2358
 
	s32 ret_val;
1687 2359
 

	
1688 2360
 
	DEBUGFUNC("e1000_write_phy_reg_82580");
...
 
@@ -1691,15 +2363,6 @@ static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
1691 2363
 
	if (ret_val)
1692 2364
 
		goto out;
1693 2365
 

	
1694
 
	/*
1695
 
	 * We config the phy address in MDICNFG register now. Same bits
1696
 
	 * as before. The values in MDIC can be written but will be
1697
 
	 * ignored. This allows us to call the old function after
1698
 
	 * configuring the PHY address in the new register
1699
 
	 */
1700
 
	mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT);
1701
 
	E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
1702
 

	
1703 2366
 
	ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
1704 2367
 

	
1705 2368
 
	hw->phy.ops.release(hw);
...
 
@@ -1709,6 +2372,45 @@ out:
1709 2372
 
}
1710 2373
 

	
1711 2374
 
/**
2375
 
 *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2376
 
 *  @hw: pointer to the HW structure
2377
 
 *
2378
 
 *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2379
 
 *  the values found in the EEPROM.  This addresses an issue in which these
2380
 
 *  bits are not restored from EEPROM after reset.
2381
 
 **/
2382
 
static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2383
 
{
2384
 
	s32 ret_val = E1000_SUCCESS;
2385
 
	u32 mdicnfg;
2386
 
	u16 nvm_data = 0;
2387
 

	
2388
 
	DEBUGFUNC("e1000_reset_mdicnfg_82580");
2389
 

	
2390
 
	if (hw->mac.type != e1000_82580)
2391
 
		goto out;
2392
 
	if (!e1000_sgmii_active_82575(hw))
2393
 
		goto out;
2394
 

	
2395
 
	ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2396
 
				   NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2397
 
				   &nvm_data);
2398
 
	if (ret_val) {
2399
 
		DEBUGOUT("NVM Read Error\n");
2400
 
		goto out;
2401
 
	}
2402
 

	
2403
 
	mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2404
 
	if (nvm_data & NVM_WORD24_EXT_MDIO)
2405
 
		mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2406
 
	if (nvm_data & NVM_WORD24_COM_MDIO)
2407
 
		mdicnfg |= E1000_MDICNFG_COM_MDIO;
2408
 
	E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2409
 
out:
2410
 
	return ret_val;
2411
 
}
2412
 

	
2413
 
/**
1712 2414
 
 *  e1000_reset_hw_82580 - Reset hardware
1713 2415
 
 *  @hw: pointer to the HW structure
1714 2416
 
 *
...
 
@@ -1720,13 +2422,17 @@ static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
1720 2422
 
	s32 ret_val = E1000_SUCCESS;
1721 2423
 
	/* BH SW mailbox bit in SW_FW_SYNC */
1722 2424
 
	u16 swmbsw_mask = E1000_SW_SYNCH_MB;
1723
 
	u32 ctrl, icr;
2425
 
	u32 ctrl;
1724 2426
 
	bool global_device_reset = hw->dev_spec._82575.global_device_reset;
1725 2427
 

	
1726 2428
 
	DEBUGFUNC("e1000_reset_hw_82580");
1727 2429
 

	
1728 2430
 
	hw->dev_spec._82575.global_device_reset = false;
1729 2431
 

	
2432
 
	/* 82580 does not reliably do global_device_reset due to hw errata */
2433
 
	if (hw->mac.type == e1000_82580)
2434
 
		global_device_reset = false;
2435
 

	
1730 2436
 
	/* Get current control state. */
1731 2437
 
	ctrl = E1000_READ_REG(hw, E1000_CTRL);
1732 2438
 

	
...
 
@@ -1747,17 +2453,18 @@ static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
1747 2453
 
	msec_delay(10);
1748 2454
 

	
1749 2455
 
	/* Determine whether or not a global dev reset is requested */
1750
 
	if (global_device_reset &&
1751
 
		e1000_acquire_swfw_sync_82575(hw, swmbsw_mask))
2456
 
	if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2457
 
	    swmbsw_mask))
1752 2458
 
			global_device_reset = false;
1753 2459
 

	
1754
 
	if (global_device_reset &&
1755
 
		!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2460
 
	if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2461
 
	    E1000_STAT_DEV_RST_SET))
1756 2462
 
		ctrl |= E1000_CTRL_DEV_RST;
1757 2463
 
	else
1758 2464
 
		ctrl |= E1000_CTRL_RST;
1759 2465
 

	
1760 2466
 
	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2467
 
	E1000_WRITE_FLUSH(hw);
1761 2468
 

	
1762 2469
 
	/* Add delay to insure DEV_RST has time to complete */
1763 2470
 
	if (global_device_reset)
...
 
@@ -1773,29 +2480,29 @@ static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
1773 2480
 
		DEBUGOUT("Auto Read Done did not complete\n");
1774 2481
 
	}
1775 2482
 

	
1776
 
	/* If EEPROM is not present, run manual init scripts */
1777
 
	if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0)
1778
 
		e1000_reset_init_script_82575(hw);
1779
 

	
1780 2483
 
	/* clear global device reset status bit */
1781 2484
 
	E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
1782 2485
 

	
1783 2486
 
	/* Clear any pending interrupt events. */
1784 2487
 
	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1785
 
	icr = E1000_READ_REG(hw, E1000_ICR);
2488
 
	E1000_READ_REG(hw, E1000_ICR);
2489
 

	
2490
 
	ret_val = e1000_reset_mdicnfg_82580(hw);
2491
 
	if (ret_val)
2492
 
		DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
1786 2493
 

	
1787 2494
 
	/* Install any alternate MAC address into RAR0 */
1788 2495
 
	ret_val = e1000_check_alt_mac_addr_generic(hw);
1789 2496
 

	
1790 2497
 
	/* Release semaphore */
1791 2498
 
	if (global_device_reset)
1792
 
		e1000_release_swfw_sync_82575(hw, swmbsw_mask);
2499
 
		hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
1793 2500
 

	
1794 2501
 
	return ret_val;
1795 2502
 
}
1796 2503
 

	
1797 2504
 
/**
1798
 
 *  e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2505
 
 *  e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
1799 2506
 
 *  @data: data received by reading RXPBS register
1800 2507
 
 *
1801 2508
 
 *  The 82580 uses a table based approach for packet buffer allocation sizes.
...
 
@@ -1813,3 +2520,1141 @@ u16 e1000_rxpbs_adjust_82580(u32 data)
1813 2520
 

	
1814 2521
 
	return ret_val;
1815 2522
 
}
2523
 

	
2524
 
/**
2525
 
 *  e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2526
 
 *  checksum
2527
 
 *  @hw: pointer to the HW structure
2528
 
 *  @offset: offset in words of the checksum protected region
2529
 
 *
2530
 
 *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2531
 
 *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2532
 
 **/
2533
 
s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2534
 
{
2535
 
	s32 ret_val = E1000_SUCCESS;
2536
 
	u16 checksum = 0;
2537
 
	u16 i, nvm_data;
2538
 

	
2539
 
	DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2540
 

	
2541
 
	for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2542
 
		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2543
 
		if (ret_val) {
2544
 
			DEBUGOUT("NVM Read Error\n");
2545
 
			goto out;
2546
 
		}
2547
 
		checksum += nvm_data;
2548
 
	}
2549
 

	
2550
 
	if (checksum != (u16) NVM_SUM) {
2551
 
		DEBUGOUT("NVM Checksum Invalid\n");
2552
 
		ret_val = -E1000_ERR_NVM;
2553
 
		goto out;
2554
 
	}
2555
 

	
2556
 
out:
2557
 
	return ret_val;
2558
 
}
2559
 

	
2560
 
/**
2561
 
 *  e1000_update_nvm_checksum_with_offset - Update EEPROM
2562
 
 *  checksum
2563
 
 *  @hw: pointer to the HW structure
2564
 
 *  @offset: offset in words of the checksum protected region
2565
 
 *
2566
 
 *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2567
 
 *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2568
 
 *  value to the EEPROM.
2569
 
 **/
2570
 
s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2571
 
{
2572
 
	s32 ret_val;
2573
 
	u16 checksum = 0;
2574
 
	u16 i, nvm_data;
2575
 

	
2576
 
	DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2577
 

	
2578
 
	for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2579
 
		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2580
 
		if (ret_val) {
2581
 
			DEBUGOUT("NVM Read Error while updating checksum.\n");
2582
 
			goto out;
2583
 
		}
2584
 
		checksum += nvm_data;
2585
 
	}
2586
 
	checksum = (u16) NVM_SUM - checksum;
2587
 
	ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2588
 
				    &checksum);
2589
 
	if (ret_val)
2590
 
		DEBUGOUT("NVM Write Error while updating checksum.\n");
2591
 

	
2592
 
out:
2593
 
	return ret_val;
2594
 
}
2595
 

	
2596
 
/**
2597
 
 *  e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2598
 
 *  @hw: pointer to the HW structure
2599
 
 *
2600
 
 *  Calculates the EEPROM section checksum by reading/adding each word of
2601
 
 *  the EEPROM and then verifies that the sum of the EEPROM is
2602
 
 *  equal to 0xBABA.
2603
 
 **/
2604
 
static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2605
 
{
2606
 
	s32 ret_val = E1000_SUCCESS;
2607
 
	u16 eeprom_regions_count = 1;
2608
 
	u16 j, nvm_data;
2609
 
	u16 nvm_offset;
2610
 

	
2611
 
	DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2612
 

	
2613
 
	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2614
 
	if (ret_val) {
2615
 
		DEBUGOUT("NVM Read Error\n");
2616
 
		goto out;
2617
 
	}
2618
 

	
2619
 
	if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2620
 
		/* if chekcsums compatibility bit is set validate checksums
2621
 
		 * for all 4 ports. */
2622
 
		eeprom_regions_count = 4;
2623
 
	}
2624
 

	
2625
 
	for (j = 0; j < eeprom_regions_count; j++) {
2626
 
		nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2627
 
		ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2628
 
								  nvm_offset);
2629
 
		if (ret_val != E1000_SUCCESS)
2630
 
			goto out;
2631
 
	}
2632
 

	
2633
 
out:
2634
 
	return ret_val;
2635
 
}
2636
 

	
2637
 
/**
2638
 
 *  e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2639
 
 *  @hw: pointer to the HW structure
2640
 
 *
2641
 
 *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2642
 
 *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2643
 
 *  checksum and writes the value to the EEPROM.
2644
 
 **/
2645
 
static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2646
 
{
2647
 
	s32 ret_val;
2648
 
	u16 j, nvm_data;
2649
 
	u16 nvm_offset;
2650
 

	
2651
 
	DEBUGFUNC("e1000_update_nvm_checksum_82580");
2652
 

	
2653
 
	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2654
 
	if (ret_val) {
2655
 
		DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2656
 
		goto out;
2657
 
	}
2658
 

	
2659
 
	if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2660
 
		/* set compatibility bit to validate checksums appropriately */
2661
 
		nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2662
 
		ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2663
 
					    &nvm_data);
2664
 
		if (ret_val) {
2665
 
			DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2666
 
			goto out;
2667
 
		}
2668
 
	}
2669
 

	
2670
 
	for (j = 0; j < 4; j++) {
2671
 
		nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2672
 
		ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2673
 
		if (ret_val)
2674
 
			goto out;
2675
 
	}
2676
 

	
2677
 
out:
2678
 
	return ret_val;
2679
 
}
2680
 

	
2681
 
/**
2682
 
 *  e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2683
 
 *  @hw: pointer to the HW structure
2684
 
 *
2685
 
 *  Calculates the EEPROM section checksum by reading/adding each word of
2686
 
 *  the EEPROM and then verifies that the sum of the EEPROM is
2687
 
 *  equal to 0xBABA.
2688
 
 **/
2689
 
static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2690
 
{
2691
 
	s32 ret_val = E1000_SUCCESS;
2692
 
	u16 j;
2693
 
	u16 nvm_offset;
2694
 

	
2695
 
	DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2696
 

	
2697
 
	for (j = 0; j < 4; j++) {
2698
 
		nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2699
 
		ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2700
 
								  nvm_offset);
2701
 
		if (ret_val != E1000_SUCCESS)
2702
 
			goto out;
2703
 
	}
2704
 

	
2705
 
out:
2706
 
	return ret_val;
2707
 
}
2708
 

	
2709
 
/**
2710
 
 *  e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2711
 
 *  @hw: pointer to the HW structure
2712
 
 *
2713
 
 *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2714
 
 *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2715
 
 *  checksum and writes the value to the EEPROM.
2716
 
 **/
2717
 
static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2718
 
{
2719
 
	s32 ret_val = E1000_SUCCESS;
2720
 
	u16 j;
2721
 
	u16 nvm_offset;
2722
 

	
2723
 
	DEBUGFUNC("e1000_update_nvm_checksum_i350");
2724
 

	
2725
 
	for (j = 0; j < 4; j++) {
2726
 
		nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2727
 
		ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2728
 
		if (ret_val != E1000_SUCCESS)
2729
 
			goto out;
2730
 
	}
2731
 

	
2732
 
out:
2733
 
	return ret_val;
2734
 
}
2735
 

	
2736
 
/**
2737
 
 *  __e1000_access_emi_reg - Read/write EMI register
2738
 
 *  @hw: pointer to the HW structure
2739
 
 *  @addr: EMI address to program
2740
 
 *  @data: pointer to value to read/write from/to the EMI address
2741
 
 *  @read: boolean flag to indicate read or write
2742
 
 **/
2743
 
static s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2744
 
				  u16 *data, bool read)
2745
 
{
2746
 
	s32 ret_val = E1000_SUCCESS;
2747
 

	
2748
 
	DEBUGFUNC("__e1000_access_emi_reg");
2749
 

	
2750
 
	ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2751
 
	if (ret_val)
2752
 
		return ret_val;
2753
 

	
2754
 
	if (read)
2755
 
		ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2756
 
	else
2757
 
		ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);